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參數(shù)資料
型號(hào)： ADV7181BCP
廠商： ANALOG DEVICES INC
元件分類： 顏色信號(hào)轉(zhuǎn)換
英文描述： Multiformat SDTV Video Decoder
中文描述： COLOR SIGNAL DECODER, QCC64
封裝： 9 X 9 MM, LEAD FREE, MO-220-VMMD, LFCSP-64
文件頁(yè)數(shù)： 57/96頁(yè)
文件大?。?/td> 873K
代理商： ADV7181BCP
ADV7181B
Interrupt Request Output Operation
Rev. 0 | Page 57 of 96
When an interrupt event occurs, the interrupt pin INTRQ
goes low with a programmable duration given by
INTRQ_DUR_SEL[1:0]
INTRQ_DURSEL[1:0], Interrupt Duration Select
Address 0x40 (Interrupt Space) [7:6]
Table 74. INTRQ_DUR_SEL
INTRQ_DURSEL[1:0]
Description
00
3 Xtal Periods (default)
01
15 Xtal Periods
10
63 Xtal Periods
11
Active until Cleared
When the “Active until Cleared” interrupt duration is selected
and the event that caused the interrupt is no longer in force, the
interrupt persists until it is masked or cleared.
For example, if the ADV7181B loses lock, an interrupt is
generated and the INTRQ pin goes low. If the ADV7181B
returns to the locked state, INTRQ
continues to drive low
until the SD_LOCK bit is either masked or cleared.
Interrupt Drive Level
The ADV7181B resets with open drain enabled and all interrupts
masked off. Therefore, INTRQ is in a high impedance state after
reset. 01 or 10 must to be written to INTRQ_OP_SEL[1:0] for a
logic level to be driven out from the INTRQ pin.
It is also possible to write to a register in the ADV7181B that
manually asserts the INTRQ pin. This bit is MPU_STIM_INTRQ.
INTRQ_OP_SEL[1:0], Interrupt Duration Select
Address 0x40 (Interrupt Space) [1:0]
Table 75. INTRQ_OP_SEL
INTRQ_OP_SEL[1:0]
Description
00
Open Drain (default)
01
Drive Low when Active
10
Drive High when active
11
Reserved
Multiple Interrupt Events
If Interrupt Event 1 occurs and then Interrupt Event 2 occurs
before the system controller has cleared or masked Interrupt
Event 1, the ADV7181B does not generate a second interrupt
signal. The system controller should check all unmasked
interrupt status bits since more than one may be active.
Macrovision Interrupt Selection Bits
The user can select between pseudo sync pulse and color stripe
detection as follows:
MV_INTRQ_SEL[1:0], Macrovision Interrupt Selection Bits
Address 0x40 (Interrupt Space) [5:4]
Table 76. MV_INTRQ_SEL
MV_INTRQ_SEL
[1:0]
Description
00
Reserved
01
Pseudo Sync Only (default)
10
Color Stripe Only
11
Either Pseudo Sync or Color Stripe
Additional information relating to the interrupt system is
detailed in Table 82.
相關(guān)PDF資料
PDF描述
ADV7181BST Multiformat SDTV Video Decoder
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ADV7183BBSTZ Multiformat SDTV Video Decoder
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ADV7181BCPZ 制造商:Analog Devices 功能描述:
ADV7181BST 制造商:Analog Devices 功能描述:Video Decoder 3ADC 9-Bit 64-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:9-BIT BIT NTSC/PAL/SECAM VIDEO DECODER - Bulk 制造商:Analog Devices 功能描述:IC VIDEO ENCODER
ADV7181C 制造商:AD 制造商全稱:Analog Devices 功能描述:10-Bit, Integrated, Multiformat SDTV Video Decoder and RGB Graphics Digitizer
ADV7181CBCPZ 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述:
ADV7181CBCPZ-REEL 制造商:AD 制造商全稱:Analog Devices 功能描述:10-Bit, Integrated, Multiformat SDTV Video Decoder and RGB Graphics Digitizer
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