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參數資料
| 型號： | ADV7190KST |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 顏色信號轉換 |
| 英文描述： | Video Encoder with Six 10-Bit DACs and Video Encoder with Six DAC Outputs |
| 中文描述： | COLOR SIGNAL ENCODER, PQFP64 |
| 封裝： | LQFP-64 |
| 文件頁數： | 32/69頁 |
| 文件大小： | 628K |
| 代理商： | ADV7190KST |
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ADV7190/ADV7191
–32–
REV. 0
Interlaced Mode Control (MR47)
This bit is used to setup the output to interlaced or noninterlaced
mode.
MODE REGISTER 5
MR5 (MR57–MR50)
(Address (SR4–SR0) = 05H)
Mode Register 5 is a 8-bit wide register. Figure 55 shows the
various operations under the control of Mode Register 5.
MR5 BIT DESCRIPTION
Y-Level Control (MR50)
This bit controls the component Y output level on the ADV7190/
ADV7191. If this bit is set (0), the encoder outputs Betacam
levels when configured in PAL or NTSC mode. If this bit is
set (1), the encoder outputs SMPTE levels when configured
in PAL or NTSC mode.
UV-Levels Control (MR51–MR52)
These bits control the component U and V output levels on
the ADV7190/ADV7191. It is possible to have UV levels with
a peak-to-peak amplitude of either 700 mV (MR52 + MR51
= 01 ) or 1000 mV (MR52 + MR51 = 10) in NTSC and PAL.
It is also possible to have default values of 934 mV for NTSC
and 700 mV for PAL (MR52 + MR51 = 00).
RGB Sync (MR53)
This bit is used to set up the RGB outputs with the sync infor-
mation encoded on all RGB outputs.
Clamp Delay Value (MR54–MR55)
These bits control the delay or advance of the CLAMP signal
in the front or back porch of the ADV7190/ADV7191. It is pos-
sible to delay or advance the pulse by zero, one, two, or three
clock cycles.
Note: Pin 51 is a multifunctional pin (
VSO
/CLAMP). CLAMP/
VSO
Select Control (MR77) has to be set accordingly.
Clamp Delay Direction (MR56)
This bit controls a positive or negative delay in the CLAMP sig-
nal. If this bit is set (1), the delay is negative. If it is set (0), the
delay is positive.
Clamp Position (MR57)
This bit controls the position of the CLAMP signal. If this bit is
set (1), the CLAMP signal is located in the back porch position.
If this bit is set (0), the CLAMP signal is located in the front
porch position.
MR57
MR56
MR55
MR54
MR53
MR52
MR51
MR50
0
1
POSITIVE
NEGATIVE
MR56
CLAMP DELAY
DIRECTION
UV LEVEL CONTROL
MR52 MR51
0 0 DEFAULT LEVELS
0
1
700mV
1
0
1000mV
1
1
RESERVED
0
1
DISABLE
ENABLE
MR53
RGB SYNC
CLAMP
POSITION
0
1
FRONT PORCH
BACK PORCH
MR57
0
1
DISABLE
ENABLE
MR50
Y LEVEL
CONTROL
CLAMP DELAY
MR55 MR54
0 0 NO DELAY
0
1
1
0
1
1
1 PCLK
2 PCLK
3 PCLK
Figure 55. Mode Register 5 (MR5)
MR47
MR46
MR45
MR44
MR43
MR42
MR41
MR40
0
1
DISABLE
ENABLE
MR46
COLOR BAR
CONTROL
CHROMINANCE
CONTROL
MR44
0
1
ENABLE COLOR
DISABLE COLOR
GENLOCK CONTROL
MR42 MR41
0 0 DISABLE GENLOCK
0
1
ENABLE SUBCARRIER
RESET PIN
1
0
TIMING RESET
1
1
ENABLE RTC PIN
0
1
DISABLE
ENABLE
MR40
VSYNC 3H CONTROL
BURST
CONTROL
0
1
ENABLE BURST
DISABLE BURST
MR45
ACTIVE VIDEO
LINE DURATION
0
1
720 PIXELS
710 PIXELS/702 PIXELS
MR43
INTERLACED
MODE CONTROL
MR47
0
1
INTERLACED
NONINTERLACED
Figure 54. Mode Register 4 (MR4)
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| ADV7191KST | Video Encoder with Six 10-Bit DACs and Video Encoder with Six DAC Outputs |
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相關代理商/技術參數 |
參數描述 |
|---|---|
| ADV7190KSTZ | 制造商:Analog Devices 功能描述:Video Encoder 6DAC 10-Bit 64-Pin LQFP |
| ADV7191 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Video Encoder with Six 10-Bit DACs and Video Encoder with Six DAC Outputs |
| ADV7191KST | 制造商:Analog Devices 功能描述:Video Encoder 6DAC 10-Bit 64-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:54M 4X STD DEF ENCODER NON-MACRO I.C. - Tape and Reel |
| ADV7191KSTZ | 制造商:Analog Devices 功能描述:Video Encoder 6DAC 10-Bit 64-Pin LQFP 制造商:Analog Devices 功能描述:IC VIDEO ENCODER |
| ADV7192 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Video Encoder with Six 10-Bit DACs, 54 MHz Oversampling and Progressive Scan Inputs |
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