- 您現在的位置：買賣IC網 > PDF目錄374047 > ADV7300A (Analog Devices, Inc.) Multiformat SD, Progressive Scan/HDTV Video Encoder with Six NSV⑩ 12-Bit DACs PDF資料下載
參數資料
| 型號： | ADV7300A |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Multiformat SD, Progressive Scan/HDTV Video Encoder with Six NSV⑩ 12-Bit DACs |
| 中文描述： | 多格式統計，逐行掃描/ HDTV視頻編碼器與六噪聲整形⑩12位DAC |
| 文件頁數： | 30/68頁 |
| 文件大小： | 1544K |
| 代理商： | ADV7300A |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁當前第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁
REV. A
–30–
ADV7300A/ADV7301A
PROGRESSIVE SCAN AT 27 MHz OR 54 MHz
YCrCb progressive scan data can be input at 27 MHz or 54 MHz.
The input data is interleaved onto a single 10-bit bus and is input
on Pins Y9–Y0. For PS Input Only Mode, the input clock
must be input on CLKIN_A. In Simultaneous SD/HD Mode,
the input clock is input on CLKIN_B.
MPEG2
DECODER
P_VSYNC
P_HSYNC
P_BLANK
CLKIN_A
Y9–Y0
INTERLACED
TO
PROGRESSIVE
YCrCb
10
3
ADV7300A/
ADV7301A
27MHz OR
54MHz
YCrCb
Figure 25. 1 10-Bit PS @ 27 MHz or 54 MHz
When the input sequence of the PS data, i.e., 10-bit interleaved
at 27 MHz, starts with Y0 data, as shown in Figure 26, PIXEL
ALIGN [Subaddress 01h] must be set to “0.” In this case, the
timing information embedded in the data stream is recognized
and the video data is transferred to the according Y channel
and CrCb channel processing blocks.
PIXEL INPUT
DATA
3FF
00
00
XY
Y0
Cb0
Y1
Cr0
CLKIN_A
Figure 26. Input Sequence in PS 10-Bit
Interleaved Mode, EAV/SAV Followed by Y0 Data
If the input sequence starts with Cb0 data as shown in Figure 27,
initially PIXEL ALIGN [Subaddress 01h] must be set to “0.”
This ensures that the ADV7300A/ADV7301A locks to the
input sequence in decoding the embedded timing information
correctly. For correct color decoding, the Pixel Align Bit
[Subaddress 01h] must then be set to “l” after a delay of one
field. The ADV7300A/ADV7301A is now in free run mode;
any changes in the timing information are ignored.
PIXEL INPUT
DATA
3FF
00
00
XY
Cb0
Y0
Cr0
Y1
CLKIN_A
Figure 27. Input Sequence in PS 10-Bit
Interleaved Mode, EAV/SAV Followed by Cb0 Data
PS 10-bit interleaved at 54 MHz must be input with separate
timing signals. EAV/SAV codes cannot be used in this mode.
相關PDF資料 |
PDF描述 |
|---|---|
| ADV7300AKST | Multiformat SD, Progressive Scan/HDTV Video Encoder with Six NSV⑩ 12-Bit DACs |
| ADV7301A | Multiformat SD, Progressive Scan/HDTV Video Encoder with Six NSV⑩ 12-Bit DACs |
| ADV7301AKST | Multiformat SD, Progressive Scan/HDTV Video Encoder with Six NSV⑩ 12-Bit DACs |
| ADV7302A | 32X2 SHROUDED VERT. HDR |
| ADV7302AKST | Sand Paper; Abrasive Grade:A VFN; Color:Maroon; Pack Quantity:6; Roll Length:30ft; Width:2" |
相關代理商/技術參數 |
參數描述 |
|---|---|
| ADV7300AKST | 制造商:Analog Devices 功能描述: |
| ADV7301A | 制造商:AD 制造商全稱:Analog Devices 功能描述:Multiformat SD, Progressive Scan/HDTV Video Encoder with Six NSV⑩ 12-Bit DACs |
| ADV7301AKST | 功能描述:IC DAC VIDEO HDTV 6-12BIT 64LQFP RoHS:否 類別:集成電路 (IC) >> 接口 - 編碼器，解碼器，轉換器 系列:- 產品變化通告:Development Systems Discontinuation 26/Apr/2011 標準包裝:1 系列:- 類型:編碼器 應用:DVB-S.2 系統 電壓 - 電源，模擬:- 電壓 - 電源，數字:- 安裝類型:- 封裝/外殼:模塊 供應商設備封裝:模塊 包裝:散裝 其它名稱:Q4645799 |
| ADV73025702 | 制造商:LG Corporation 功能描述:Frame Assembly |
| ADV73025801 | 制造商:LG Corporation 功能描述:Frame Assembly |
發布緊急采購，3分鐘左右您將得到回復。