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參數資料
型號: ADV7300A
廠商: Analog Devices, Inc.
英文描述: Multiformat SD, Progressive Scan/HDTV Video Encoder with Six NSV⑩ 12-Bit DACs
中文描述: 多格式統計,逐行掃描/ HDTV視頻編碼器與六噪聲整形⑩12位DAC
文件頁數: 33/68頁
文件大小: 1544K
代理商: ADV7300A
REV. A
ADV7300A/ADV7301A
–33–
TIMING MODES
HD Async Timing Mode
[Subaddress 10h, Bits 3–2]
For any input data that does not conform to SMPTE293M,
SMPTE274M, SMPTE296M, or ITU-R.BT1358 standards,
an Asynchronous Timing Mode can be used to interface to the
ADV7300A/ADV7301A. Timing control signals for HSYNC,
VSYNC, and BLANK have to be programmed by the user.
Macrovision is not available in Async Timing Mode.
Figure 28 shows an example of how to program the ADV7300A/
ADV7301A to accept a different high definition standard, other
than SMPTE293M, SMPTE274M, SMPTE296M, or
ITU-R.BT1358 standards.
Table XIV must be followed when programming the control sig-
nals in Async Timing Mode.
HD Timing Reset
A timing reset is achieved in setting the HD Timing Reset Con-
trol Bit at Address 14h from “0” to “1.” In this state, the
horizontal and vertical counters will remain reset. On setting
this bit back to “0,” the internal counters will again commence
counting. The minimum time the pin has to be held high is one
clock cycle; otherwise, this reset signal might not be recognized.
This timing reset applies to the HD timing counters only.
SD Timing
Real-time Control, Subcarrier Reset, Timing Reset
[Subaddress 44h, Bits 2–1]
Together with the RTC_SCR_TR pin and SD Mode Register 3
[Address 44h, Bits 1–2], the ADV7300A/ADV7301A can be
used in Timing Reset Mode, Subcarrier Phase Reset Mode,
or RTC Mode.
a. A timing reset is achieved in a low-to-high transition on the
RTC_SCR_TR pin (Pin 31). In this state, the horizontal and
vertical counters will remain reset. On releasing this pin (set
to low), the internal counters will again commence counting.
The minimum time the pin has to be held high is one clock
cycle; otherwise, this reset signal might not be recognized. This
timing reset applies to the SD timing counters only.
b. Subcarrier phase reset, a low-to-high transition on the
RTC_SCR_TR pin (Pin 31), will reset the subcarrier phase
to zero when the SD RTC/TR/SCR control bits at Address 44h
are set to “01.” This reset signal will have to be held high for
a minimum of one clock cycle. Since the Field Counter is
not reset, it is recommended to apply the reset in Field 7
(PAL). The reset of the phase will then occur on the next field
by being correctly lined up with the internal counters. The
Field Count Register at Address 7Bh can be used to identify
the number of the active field.
c. In RTC Mode, the ADV7300A/ADV7301A can be used to
lock to an external video source. The Real-time Control Mode
allows the ADV7300A/ADV7301A to automatically alter the
subcarrier frequency to compensate for line length variations.
When the part is connected to a device that outputs a digital
data stream in the RTC format (such as a ADV7185 video
decoder; see Figure 29), the part will automatically change to
the compensated subcarrier frequency on a line-by-line basis.
This digital data stream is 67 bits wide and the subcarrier is
contained in Bits 0 to 21. Each bit is two clock cycles long.
00h should be written into all four Subcarrier Frequency
Registers when using this mode.
CLK
ACTIVE VIDEO
PROGRAMMABLE
INPUT TIMING
ANALOG
OUTPUT
a
b
c
d
81
66
66
243
1920
HORIZONTAL SYNC
e
P_HSYNC
P_VSYNC
P_BLANK
*
*
SET ADDRESS 10h, BIT 6 TO “1”
Figure 28. Async Timing Mode, Programming Input Control Signals for SMPTE295M Compatibility
相關PDF資料
PDF描述
ADV7300AKST Multiformat SD, Progressive Scan/HDTV Video Encoder with Six NSV⑩ 12-Bit DACs
ADV7301A Multiformat SD, Progressive Scan/HDTV Video Encoder with Six NSV⑩ 12-Bit DACs
ADV7301AKST Multiformat SD, Progressive Scan/HDTV Video Encoder with Six NSV⑩ 12-Bit DACs
ADV7302A 32X2 SHROUDED VERT. HDR
ADV7302AKST Sand Paper; Abrasive Grade:A VFN; Color:Maroon; Pack Quantity:6; Roll Length:30ft; Width:2"
相關代理商/技術參數
參數描述
ADV7300AKST 制造商:Analog Devices 功能描述:
ADV7301A 制造商:AD 制造商全稱:Analog Devices 功能描述:Multiformat SD, Progressive Scan/HDTV Video Encoder with Six NSV⑩ 12-Bit DACs
ADV7301AKST 功能描述:IC DAC VIDEO HDTV 6-12BIT 64LQFP RoHS:否 類別:集成電路 (IC) >> 接口 - 編碼器,解碼器,轉換器 系列:- 產品變化通告:Development Systems Discontinuation 26/Apr/2011 標準包裝:1 系列:- 類型:編碼器 應用:DVB-S.2 系統 電壓 - 電源,模擬:- 電壓 - 電源,數字:- 安裝類型:- 封裝/外殼:模塊 供應商設備封裝:模塊 包裝:散裝 其它名稱:Q4645799
ADV73025702 制造商:LG Corporation 功能描述:Frame Assembly
ADV73025801 制造商:LG Corporation 功能描述:Frame Assembly
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