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參數資料
| 型號： | ADV7301A |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Multiformat SD, Progressive Scan/HDTV Video Encoder with Six NSV⑩ 12-Bit DACs |
| 中文描述： | 多格式統計，逐行掃描/ HDTV視頻編碼器與六噪聲整形⑩12位DAC |
| 文件頁數： | 13/68頁 |
| 文件大小： | 1544K |
| 代理商： | ADV7301A |
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REV. A
ADV7300A/ADV7301A
–13–
Pin No.
Mnemonic
Input/Output
Function
14–18, 26–30
C0–C9
I
10-Bit Progressive Scan/HDTV Input Port for CrCb color data in 4:2:2 Input
Mode. In 4:4:4 Input Mode, this input port is used for the Cb (Blue/U) data.
The LSBs are set up on Pins C0 and C1. In Default Mode, the input on this
port is output on DAC E.
This input pin must be tied high (V
DD_IO
) for the ADV7300A/ADV7301A to
interface over the I
2
C port.
TTL Address Input. This signal sets up the LSB of the MPU address. When
this pin is tied low, the I
2
C filter is activated, which reduces noise on the I
2
C interface.
MPU Port Serial Data Input/Output
MPU Port Serial Interface Clock Input
Video Horizontal Sync Control Signal for HD Sync in Simultaneous SD/HD
Mode and HD Only Mode
Video Vertical Sync Control Signal for HD Sync in Simultaneous SD/HD
Mode and HD Only Mode
Video Blanking Control Signal for HD Sync in Simultaneous SD/HD Mode
and HD Only Mode
Multifunctional Input: Realtime Control (RTC) Input, Timing Reset Input,
and Subcarrier Reset Input
Pixel Clock Input for HD Only or SD Only Modes
This input resets the on-chip timing generator and sets the ADV7300A/
ADV7301A into default register setting. Reset is an active low signal.
External Loop Filter for the internal PLL
A 760
resistor must be connected from this pin to AGND and is used to
control the amplitudes of the DAC outputs.
Compensation Pin for DACs. Connect 0.1
μ
F capacitor from COMP pin to V
AA
.
In SD Only Mode: Chroma/Red/V Analog Output, in HD Only Mode and
Simultaneous HD/SD: Pb/Blue (HD) Analog Output
In SD Only Mode: Luma/Blue/U Analog Output, in HD Only Mode and
Simultaneous HD/SD: Pr/Red (HD) Analog Output
In SD Only Mode: CVBS/Green/Y Analog Output, in HD Only Mode and
Simultaneous HD/SD: Y/Green (HD) Analog Output
Analog Ground
Analog Power Supply
Chroma/Red/V SD Analog Output
Luma/Blue/U SD Analog Output
CVBS/Green/Y SD Analog Output
Optional External Voltage Reference Input for DACs or Voltage Reference
Output (1.235 V)
Video Blanking Control Signal for SD
Video Vertical Control Signal for SD. Option to output SD VSYNC or SD
HSYNC in SD Slave Mode 0 and/or any HD Mode.
Video Horizontal Control Signal for SD. Option to output SD HSYNC or
HD HSYNC in SD Slave Mode 0 and/or any HD Mode.
10-Bit Standard Definition Input Port or Progressive Scan/HDTV Input Port
for Cr (Red/V) color data in 4:4:4 Input Mode. The LSBs are set up on Pins
S0 and S1. In Default Mode, the input on this port is output on DAC F.
Pixel Clock Input. Requires a 27 MHz reference clock for Progressive Scan
Mode or a 74.25 MHz (74.1758 MHz) reference clock in HDTV Mode. This
clock input pin is only used in Simultaneous SD/HD Mode.
Digital Ground
19
I
2
C
I
20
ALSB
I/O
21
22
23
SDA
SCLK
P_HSYNC
I/O
I
I
24
P_VSYNC
I
25
P_BLANK
I
31
RTC_SCR_TR
I
32
33
CLKIN_A
RESET
I
I
34
35, 47
EXT_LF
R
SET2, 1
I
I
36, 45
37
COMP2, 1
DAC F
O
O
38
DAC E
O
39
DAC D
O
40
41
42
43
44
46
AGND
V
AA
DAC C
DAC B
DAC A
V
REF
G
P
O
O
O
I/O
48
49
S_BLANK
S_VSYNC
I/O
I/O
50
S_HSYNC
I/O
51–55, 58–62
S0–S9
I
63
CLKIN_B
I
64
GND_IO
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