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參數資料
| 型號： | ADV7301AKST |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 顏色信號轉換 |
| 英文描述： | Multiformat SD, Progressive Scan/HDTV Video Encoder with Six NSV⑩ 12-Bit DACs |
| 中文描述： | COLOR SIGNAL ENCODER, PQFP64 |
| 封裝： | PLASTIC, MS-026BCD, LQFP-64 |
| 文件頁數： | 30/68頁 |
| 文件大小： | 1544K |
| 代理商： | ADV7301AKST |
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REV. A
–30–
ADV7300A/ADV7301A
PROGRESSIVE SCAN AT 27 MHz OR 54 MHz
YCrCb progressive scan data can be input at 27 MHz or 54 MHz.
The input data is interleaved onto a single 10-bit bus and is input
on Pins Y9–Y0. For PS Input Only Mode, the input clock
must be input on CLKIN_A. In Simultaneous SD/HD Mode,
the input clock is input on CLKIN_B.
MPEG2
DECODER
P_VSYNC
P_HSYNC
P_BLANK
CLKIN_A
Y9–Y0
INTERLACED
TO
PROGRESSIVE
YCrCb
10
3
ADV7300A/
ADV7301A
27MHz OR
54MHz
YCrCb
Figure 25. 1 10-Bit PS @ 27 MHz or 54 MHz
When the input sequence of the PS data, i.e., 10-bit interleaved
at 27 MHz, starts with Y0 data, as shown in Figure 26, PIXEL
ALIGN [Subaddress 01h] must be set to “0.” In this case, the
timing information embedded in the data stream is recognized
and the video data is transferred to the according Y channel
and CrCb channel processing blocks.
PIXEL INPUT
DATA
3FF
00
00
XY
Y0
Cb0
Y1
Cr0
CLKIN_A
Figure 26. Input Sequence in PS 10-Bit
Interleaved Mode, EAV/SAV Followed by Y0 Data
If the input sequence starts with Cb0 data as shown in Figure 27,
initially PIXEL ALIGN [Subaddress 01h] must be set to “0.”
This ensures that the ADV7300A/ADV7301A locks to the
input sequence in decoding the embedded timing information
correctly. For correct color decoding, the Pixel Align Bit
[Subaddress 01h] must then be set to “l” after a delay of one
field. The ADV7300A/ADV7301A is now in free run mode;
any changes in the timing information are ignored.
PIXEL INPUT
DATA
3FF
00
00
XY
Cb0
Y0
Cr0
Y1
CLKIN_A
Figure 27. Input Sequence in PS 10-Bit
Interleaved Mode, EAV/SAV Followed by Cb0 Data
PS 10-bit interleaved at 54 MHz must be input with separate
timing signals. EAV/SAV codes cannot be used in this mode.
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