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參數資料
| 型號： | ADV7301AKST |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 顏色信號轉換 |
| 英文描述： | Multiformat SD, Progressive Scan/HDTV Video Encoder with Six NSV⑩ 12-Bit DACs |
| 中文描述： | COLOR SIGNAL ENCODER, PQFP64 |
| 封裝： | PLASTIC, MS-026BCD, LQFP-64 |
| 文件頁數： | 5/68頁 |
| 文件大小： | 1544K |
| 代理商： | ADV7301AKST |
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REV. A
ADV7300A/ADV7301A
–5–
TIMING SPECIFICATIONS
Parameter
MPU PORT
1
SCLOCK Frequency
SCLOCK High Pulsewidth, t
1
SCLOCK Low Pulsewidth, t
2
Hold Time (Start Condition), t
3
Min
Typ
Max
Unit
Test Conditions
0
0.6
1.3
0.6
400
kHz
μ
s
μ
s
μ
s
First Clock Generated after
This Period
Relevant for Repeated Start
Condition
Setup Time (Start Condition), t
4
0.6
μ
s
Data Setup Time, t
5
SDATA, SCLOCK Rise Time, t
6
SDATA, SCLOCK Fall Time, t
7
Setup Time (Stop Condition), t
8
RESET
Low Time
100
ns
ns
ns
μ
s
ns
300
300
0.6
100
ANALOG OUTPUTS
Analog Output Delay
2
Output Skew
CLOCK CONTROL AND PIXEL PORT
3
f
CLK
f
CLK
Clock High Time, t
9
Clock Low Time, t
10
Data Setup Time, t
11
Data Hold Time, t
12
Output Access Time, t
13
Output Hold Time, t
14
Pipeline Delay
8
1
ns
ns
27
MHz
MHz
% 1 clkcycle
% 1 clkcycle
ns
ns
ns
ns
clkcycles
clkcycles
clkcycles
clkcycles
Progressive Scan Mode
HDTV Mode/Async Mode
81
40
40
2.0
2.0
14
4.0
61
62.5
66.5
33
SD [2 ]
SD [8 ]
SD Component Filter [8 ]
PS [1 ], HD [1 ], Async
Timing Mode
PS [4 ]
HD [2 ]
43.5
36
clkcycles
clkcycles
NOTES
1
Guaranteed by characterization.
2
Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of DAC output full-scale transition.
3
Data: C[9:0]; S[9:0]; Y[9:0]
Control:
P_HSYNC
;
P_ VSYNC
; P_BLANK;
S_HSYNC
;
S_VSYNC
;
S_BLANK
Specifications subject to change without notice.
(V
AA
= V
DD
= 2.375 V–2.625 V, V
= 2.375 V–3.600 V, V
REF
= 1.235 V, R
SET
= 760
T
MIN
to T
MAX
(0 C to 70 C), unless otherwise noted.)
, R
LOAD
= 150
,
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