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參數(shù)資料
| 型號： | ADV7303AKST |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 顏色信號轉(zhuǎn)換 |
| 英文描述： | Sand Paper; Abrasive Grade:T; Color:White; Pack Quantity:3; Roll Length:30ft; Width:4" |
| 中文描述： | COLOR SIGNAL ENCODER, PQFP64 |
| 封裝： | PLASTIC, MS-026BCD, LQFP-64 |
| 文件頁數(shù)： | 3/68頁 |
| 文件大小： | 1177K |
| 代理商： | ADV7303AKST |
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REV. A
–3–
ADV7302A/ADV7303A–SPECIFICATIONS
(V
AA
= V
DD
= 2.375V–2.625V, V
DD_IO
= 2.375V–3.600V, V
REF
= 1.235V, R
SET
= 760 , R
LOAD
= 150 , T
MIN
to T
MAX
(0 C to 70 C), unless otherwise noted.)
Parameter
STATIC PERFORMANCE
1
Resolution
Integral Nonlinearity
Differential Nonlinearity, +ve
2
Differential Nonlinearity, –ve
2
Min
Typ
Max
Unit
Test Conditions
11
±
1.0
0.125
1.0
Bits
LSB
LSB
LSB
V
AA
= 2.5 V
V
AA
= 2.5 V
V
AA
= 2.5 V
DIGITAL OUTPUTS
Output Low Voltage, V
OL
Output High Voltage, V
OH
Three-State Leakage Current
Three-State Output Capacitance
0.4 [0.4]
3
V
V
μ
A
pF
I
SINK
= 3.2 mA
I
SOURCE
= 400
μ
A
V
IN
= 0.4 V, 2.4 V
2.4 [2.0]
3
±
1.0
2
DIGITAL AND CONTROL INPUTS
Input High Voltage, V
IH
Input Low Voltage, V
IL
Input Leakage Current
Input Capacitance, C
IN
ANALOG OUTPUTS
Full-Scale Output Current
Output Current Range
Full-Scale Output Current
Output Current Range
DAC to DAC Matching
Output Compliance Range, V
OC
Output Capacitance, C
OUT
VOLTAGE REFERENCE
Reference Range, V
REF
POWER REQUIREMENTS
Normal Power Mode
I
DD4
2
V
V
μ
A
pF
0.8
1
2
V
IN
= 2.4 V
8.2
8.2
4.1
4.1
8.7
8.7
4.35
4.35
2.0
1.0
7
9.2
9.2
4.6
4.6
mA
mA
mA
mA
%
V
pF
R
SET1, 2
= 1520
R
SET1, 2
= 1520
0
1.4
1.15
1.235
1.3
V
93
52
84
90
99
108
0.2
70
37
mA
mA
mA
mA
mA
mA
mA
mA
mA
SD Only [8 ]
PS Only [4 ]
HDTV Only [2 ]
SD and PS
SD [8 ] and HDTV
SD and HDTV [2 ]
110
I
DD_IO
I
AA5, 6
75
45
R
SET1, 2
= 1520
Sleep Mode
I
DD
I
AA
I
DD_IO
Power Supply Rejection Ratio
130
10
110
0.01
μ
A
μ
A
μ
A
%/%
NOTES
1
Oversampling disabled. Static DAC performance will be improved with increased oversampling ratios.
2
DNL measures the deviation of the actual DAC o/p voltage step from the ideal. For +ve DNL, the actual step value lies above the ideal step value; for –ve DNL, the
actual step values lie below the ideal step value.
3
Value in brackets for V
= 2.375 V to 2.750 V.
4
I
DD
or the circuit current is the continuous current required to drive the digital core without the I
.
5
I
is the total current required to supply all DACs including the V
REF
circuitry and the PLL circuitry.
6
All DACs on.
Specifications subject to change without notice.
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