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參數資料
| 型號： | ADV7303AKST |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 顏色信號轉換 |
| 英文描述： | Sand Paper; Abrasive Grade:T; Color:White; Pack Quantity:3; Roll Length:30ft; Width:4" |
| 中文描述： | COLOR SIGNAL ENCODER, PQFP64 |
| 封裝： | PLASTIC, MS-026BCD, LQFP-64 |
| 文件頁數： | 51/68頁 |
| 文件大小： | 1177K |
| 代理商： | ADV7303AKST |
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REV. A
ADV7302A/ADV7303A
–51–
To avoid crosstalk between the DAC outputs, it is recommended
to leave as much space as possible between the tracks of the
individual DAC output pins.
Supply Decoupling
Noise on the analog power plane can be further reduced by the
use of decoupling capacitors. Optimum performance is achieved
by the use of 0.1
μ
F ceramic capacitors. Each of the group of
V
AA
, V
DD,
or V
DD_IO
Pins should be individually decoupled to
ground. This should be done by placing the capacitors as close
as possible to the device with the capacitor leads as short as
possible, thus minimizing lead inductance.
Digital Signal Interconnect
The digital signal lines should be isolated as much as possible
from the analog outputs and other analog circuitry. Digital
signal lines should not overlay the analog power plane. Due to
the high clock rates used, long clock lines to the ADV7302A/
ADV7303A should be avoided to minimize noise pickup. Any
active pull-up termination resistors for the digital inputs should
be connected to the digital power plane and not the analog
power plane.
Analog Signal Interconnect
The ADV7302A/ADV7303A should be located as close as pos-
sible to the output connectors, thus minimizing noise pickup
and reflections due to impedance mismatch. For optimum per-
formance, the analog outputs should each be source and load
terminated, as shown in Figure 79. The termination resistors
should be as close as possible to the ADV7302A/ADV7303A to
minimize reflections.
Any unused inputs should be tied to ground.
S_HSYNC
S0–S7
S_VSYNC
S BLANK
C0–C7
Y0–Y7
P_HSYNC
P_VSYNC
P_BLANK
RESET
CLKIN_B
CLKIN_A
EXT_LF
GND_IO AGND DGND
R
SET2
R
SET1
ALSB
I
2
C
SCLK
DAC F
DAC E
DAC D
DAC C
DAC B
DAC A
V
REF
V
DD_IO
V
DD
V
AA
COMP2
COMP1
150
150
150
150
SDA
11, 57
760
760
5k
V
DD_IO
5k
V
DD_IO
5k
V
DD_IO
HD Pr/RED
5k
V
DD_IO
HD Pb/BLUE
HD Y/GREEN
SD CHROMA/RED/V
SD LUMA/BLUE/U
SD CVBS/GREEN/Y
3.9nF
680R
820pF
V
AA
4.7 F
6.3V
150
V
AA
UNUSED INPUTS SHOULD BE GROUNDED
47k
V
AA
V
AA
0.1 F
0.1 F
0.1 F
V
AA
0.1 F
10nF
0.1 F
10nF
10nF
10, 56
V
DD_IO
V
DD
I
2
C
BUS
ADV7302A/
ADV7303A
POWER SUPPLY DECOUPLING FOR
EACH POWER SUPPLY GROUP
150
2, 3, 14,
15, 51, 52, 64
Figure 79. Circuit Layout
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