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參數資料
| 型號： | ADV7392BCPZ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 顏色信號轉換 |
| 英文描述： | Low Power, Chip Scale 10-Bit SD/HD Video Encoder |
| 中文描述： | COLOR SIGNAL ENCODER, QCC40 |
| 封裝： | 6 X 6 MM, ROHS COMPLIANT, MO-220VJJD-2, LFSCP-40 |
| 文件頁數： | 66/96頁 |
| 文件大小： | 1209K |
| 代理商： | ADV7392BCPZ |
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ADV7390/ADV7391/ADV7392/ADV7393
APPENDIX 1–COPY GENERATION MANAGEMENT SYSTEM
SD CGMS
Subaddress 0x99 to Subaddress 0x9B
The ADV739x supports copy generation management system
(CGMS) that conforms to the EIAJ CPR-1204 and ARIB TR-B15
standards. CGMS data is transmitted on Line 20 of the odd fields
and Line 283 of even fields. Subaddress 0x99, Bits[6:5] control
whether CGMS data is output on odd or even fields or both.
SD CGMS data can only be transmitted when the ADV739x is
configured in NTSC mode. The CGMS data is 20 bits long. The
CGMS data is preceded by a reference pulse of the same
amplitude and duration as a CGMS bit (see Figure 93).
ED CGMS
Subaddress 0x41 to Subaddress 0x43
Subaddress 0x5E to Subaddress 0x6E
525p
The ADV739x supports copy generation management system
(CGMS) in 525p mode in accordance with EIAJ CPR-1204-1.
When ED CGMS is enabled (Subaddress 0x32, Bit 6 = 1), 525p
CGMS data is inserted on Line 41. The 525p CGMS data
registers are at Subaddress 0x41, Subaddress 0x42, and
Subaddress 0x43.
The ADV739x also supports CGMS Type B packets in 525p
mode in accordance with CEA-805-A.
When ED CGMS Type B is enabled (Subaddress 0x5E, Bit 0 = 1),
525p CGMS Type B data is inserted on Line 40. The 525p CGMS
Type B data registers are at Subaddress 0x5E to Subaddress 0x6E.
625p
The ADV739x supports copy generation management system
(CGMS) in 625p mode in accordance with IEC 62375 (2004).
When ED CGMS is enabled (Subaddress 0x32, Bit 6 = 1), 625p
CGMS data is inserted on Line 43. The 625p CGMS data
registers are at Subaddress 0x42 and Subaddress 0x43.
HD CGMS
Subaddress 0x41 to Subaddress 0x43
Subaddress 0x5E to Subaddress 0x6E
The ADV739x supports copy generation management system
(CGMS) in HD mode (720p and 1080i) in accordance with
EIAJ CPR-1204-2.
When HD CGMS is enabled (Subaddress 0x32, Bit 6 = 1), 720p
CGMS data is applied to Line 24 of the luminance vertical
blanking interval.
Rev. 0 | Page 66 of 96
When HD CGMS is enabled (Subaddress 0x32, Bit 6 = 1), 1080i
CGMS data is applied to Line 19 and Line 582 of the luminance
vertical blanking interval.
The HD CGMS data registers are at Subaddress 0x41,
Subaddress 0x42, and Subaddress 0x43.
The ADV739x also supports CGMS Type B packets in HD
mode (720p and 1080i) in accordance with CEA-805-A.
When HD CGMS Type B is enabled (Subaddress 0x5E, Bit 0 = 1),
720p CGMS data is applied to Line 23 of the luminance vertical
blanking interval.
When HD CGMS Type B is enabled (Subaddress 0x5E, Bit 0 = 1),
1080i CGMS data is applied to Line 18 and Line 581 of the
luminance vertical blanking interval.
The HD CGMS Type B data registers are at Subaddress 0x5E to
Subaddress 0x6E.
CGMS CRC FUNCTIONALITY
If SD CGMS CRC (Subaddress 0x99, Bit 4) or ED/HD CGMS
CRC (Subaddress 0x32, Bit 7) is enabled, the upper six CGMS
data bits (C19 to C14) that comprise the 6-bit CRC check
sequence are automatically calculated on the ADV739x. This
calculation is based on the lower 14 bits (C13 to C0) of the data
in the CGMS data registers, and the result is output with the
remaining 14 bits to form the complete 20 bits of the CGMS
data. The calculation of the CRC sequence is based on the
polynomial x
6
+ x + 1 with a preset value of 111111.
If SD CGMS CRC or ED/HD CGMS CRC is disabled, all 20 bits
(C19 to C0) are output directly from the CGMS registers (CRC
must be calculated by the user manually).
If ED/HD CGMS Type B CRC (Subaddress 0x5E, Bit 1) is
enabled, the upper six CGMS Type B data bits (P122 to P127)
that comprise the 6-bit CRC check sequence are automatically
calculated on the ADV739x. This calculation is based on the
lower 128 bits (H0 to H5 and P0 to P121) of the data in the
CGMS Type B data registers. The result is output with the
remaining 128 bits to form the complete 134 bits of the CGMS
Type B data. The calculation of the CRC sequence is based on
the polynomial x
6
+ x + 1 with a preset value of 111111.
If ED/HD CGMS Type B CRC is disabled, all 134 bits (H0 to H5
and P0 to P127) are output directly from the CGMS Type B
registers (CRC must be calculated by the user manually).
相關PDF資料 |
PDF描述 |
|---|---|
| ADV7392BCPZ-REEL | Low Power, Chip Scale 10-Bit SD/HD Video Encoder |
| ADV7392EBZ | Low Power, Chip Scale 10-Bit SD/HD Video Encoder |
| ADV7393 | Low Power, Chip Scale 10-Bit SD/HD Video Encoder |
| ADV7393BCPZ | Low Power, Chip Scale 10-Bit SD/HD Video Encoder |
| ADV7393BCPZ-REEL | Low Power, Chip Scale 10-Bit SD/HD Video Encoder |
相關代理商/技術參數 |
參數描述 |
|---|---|
| ADV7392BCPZ-3REEL | 功能描述:Video Encoder IC DVD, Game Consoles, Media Players 40-LFCSP-WQ (6x6) 制造商:analog devices inc. 系列:- 包裝:帶卷（TR） 零件狀態:有效 類型:視頻編碼器 應用:DVD，游戲控制臺，媒體播放器 電壓 - 電源，模擬:2.6 V ~ 3.46 V 電壓 - 電源，數字:1.71 V ~ 1.89 V 安裝類型:表面貼裝 封裝/外殼:40-WFQFN 裸露焊盤，CSP 供應商器件封裝:40-LFCSP-WQ（6x6） 標準包裝:2,500 |
| ADV7392BCPZ-REEL | 制造商:AD 制造商全稱:Analog Devices 功能描述:Low Power, Chip Scale 10-Bit SD/HD Video Encoder |
| ADV7392EBZ | 制造商:AD 制造商全稱:Analog Devices 功能描述:Low Power, Chip Scale 10-Bit SD/HD Video Encoder |
| ADV7392WBCPZ | 制造商:Analog Devices 功能描述: |
| ADV7392WBCPZ-REEL | 制造商:Analog Devices 功能描述: |
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