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參數(shù)資料
| 型號： | AS4LC1M16E5 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 3V 1M X 6 CMOS DRAM (EDO) |
| 中文描述： | 3V的100萬× 6的CMOS的DRAM（江戶） |
| 文件頁數(shù)： | 2/22頁 |
| 文件大小： | 604K |
| 代理商： | AS4LC1M16E5 |
AS4LC1M16E5
4/11/01
Alliance Semiconductor
2
Functional description
The AS4LC1M16E5 is a high performance 16-megabit CMOS Dynamic Random Access Memory (DRAM) organized as 1,048,576 words × 16
bits. The device is fabricated using advanced CMOS technology and innovative design techniques resulting in high speed, extremely low power
and wide operating margins at component and system levels. The Alliance 16Mb DRAM family is optimized for use as main memory in
personal and portable PCs, workstations, and multimedia and router switch applications.
The AS4LC1M16E5 features hyper page mode operation where read and write operations within a single row (or page) can be executed at very
high speed by toggling column addresses within that row. Row and column addresses are alternately latched into input buffers using the falling
edge of RAS and xCAS inputs, respectively. Also, RAS is used to make the column address latch transparent, enabling application of column
addresses prior to xCAS assertion. The AS4LC1M16E5 provides dual UCAS and LCAS for independent byte control of read and write access.
Extended data out (EDO), also known as 'hyper-page mode,' enables high speed operation. In contrast to 'fast-page mode' devices, data remains
active on outputs after xCAS is de-asserted high, giving system logic more time to latch the data. Use OE and WE to control output impedance
and prevent bus contention during read-modify-write and shared bus applications. Outputs also go to high impedance at the last occurrance of
RAS and xCAS going high.
Refresh on the 1024 address combinations of A0 to A9 must be performed every 16 ms using:
RAS-only refresh: RAS is asserted while xCAS is held high. Each of the 1024 rows must be strobed. Outputs remain high impedence.
Hidden refresh: xCAS is held low while RAS is toggled. Outputs remain low impedence with previous valid data.
CAS-before-RAS refresh (CBR): At least one xCAS is asserted prior to RAS. Refresh address is generated internally.
Outputs are high-impedence (OE and WE are don't care).
Normal read or write cycles refresh the row being accessed.
Self-refresh cycles
The AS4LC1M16E5 is available in the standard 42-pin plastic SOJ and 44/50-pin TSOP II packages, respectively. The AS4LC1M16E5 device
operates with a single power supply of 3V ± 0.3V and provides TTL compatible inputs and outputs.
Logic block diagram
Recommended operating conditions
Parameter
V
IL
min -3.0V for pulse widths less than 5 ns.
Recommended operating conditions apply throughout this document unless otherwise specified.
Symbol
Min
Nominal
Max
Unit
Supply voltage
V
CC
GND
3.0
3.3
3.6
V
0.0
0.0
0.0
V
Input voltage
V
IH
V
IL
2.0
–0.5
–
5.5
V
–
0.8
V
Ambient operating temperature
Commercial
T
A
0
–
70
°C
Industrial
-40
–
85
RAS clock
generator
R
c
1024 × 1024 × 16
Array
(16,777,216)
Sense amp
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
V
CC
GND
A
R
Column decoder
Substrate bias
generator
Data
DQ
buffers
OE
RAS
UCAS
LCAS
WE clock
generator
WE
DQ1 to DQ16
CAS clock
generator
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AS4LC1M16E5-50JC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:3V 1M X 6 CMOS DRAM (EDO) |
| AS4LC1M16E5-50JI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:3V 1M X 6 CMOS DRAM (EDO) |
| AS4LC1M16E5-50TC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:3V 1M X 6 CMOS DRAM (EDO) |
| AS4LC1M16E5-50TI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:3V 1M X 6 CMOS DRAM (EDO) |
| AS4LC1M16E5-60JC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:3V 1M X 6 CMOS DRAM (EDO) |
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