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參數資料
| 型號： | AS7C33512PFD32A-200BI |
| 廠商： | ALLIANCE SEMICONDUCTOR CORP |
| 元件分類： | SRAM |
| 英文描述： | 512K X 32 STANDARD SRAM, 3 ns, PBGA119 |
| 封裝： | BGA-119 |
| 文件頁數： | 1/2頁 |
| 文件大小： | 53K |
| 代理商： | AS7C33512PFD32A-200BI |
July 2001
Advanced Information
Copyright Alliance Semiconductor. All rights reserved.
AS7C33512PFD32A
AS7C33512PFD36A
8/27/01; v.0.9.1
Alliance Semiconductor
1 of 2
3.3V 512K
×××× 32/36 pipeline burst synchronous SRAM
Features
Organization: 524,288 words x 32/36 bits
Fast clock speeds to 200MHz in LVTTL/LVCMOS
Fast clock to data access: 3.0/3.5/4.0 ns
Fast OE access time: 3.0/3.5/4.0 ns
Fully synchronous register-to-register operation
Single register “Flow-through” mode
Dual-cycle deselect
- Single-cycle deselect also available ( AS7C33512PFS32A/
AS7C33512PFS36A)
Pentium* compatible architecture and timing
Asynchronous output enable control
100-pin TQFP package
119-Ball BGA (7 x 17 Ball Grid Array Package)
Byte write enables
Multiple chip enables for easy expansion
3.3 core power supply
2.5V or 3.3V I/O operation with separate VDDQ
NTD* pipeline architecture available
(AS7C33512NTD32A/ AS7C33512NTD36A)
Logic Block Diagram:
*Pentium is a registered trademark of Intel Corporation. NTD is a
trademark of Alliance Semiconductor Corporation. All trademarks
mentioned in this document are the property of their respective owners.
Pin Arrangements:
DQPc/NC
DQc
VDDQ
VSSQ
DQc
VSSQ
VDDQ
DQc
FT
VDD
NC
VSS
DQd
VDDQ
VSSQ
DQd
VSSQ
VDDQ
DQd
DQPd/NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQPb/NC
DQb
VDDQ
VSSQ
DQb
VSSQ
VDDQ
DQb
VSS
ZZ
DQa
VDDQ
VSSQ
DQa
VSSQ
VDDQ
DQa
DQPa/NC
LBO
A5
A4
A3
A2
A1
A0
NC
V
SS
V
DD
A18
A17
A10
A11
A12
A13
A14
A15
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
A6
A7
CE0
CE1
BW
d
BW
c
BW
b
BW
a
CE2
V
DD
V
SS
CLK
GWE
BW
E
OE
AD
SC
AD
SP
AD
V
A8
A9
NC
VDD
A16
Note: Pins 1,30,51,80 are NC for ×32
TQFP 14 × 20 mm
512K x 32A/36A
Q0
Q1
512K × 32/36
Memory
array
Burst logic
CLK
CLR
CE
Address
DQ
CE
CLK
DQd
CLK
DQ
Byte write
registers
register
DQc
CLK
DQ
Byte write
registers
DQb
CLK
DQ
Byte write
registers
DQa
CLK
DQ
Byte write
registers
Enable
CLK
DQ
register
Enable
CLK
DQ
delay
register
CE
Output
registers
Input
registers
Power
down
DATA [35:0]
4
36/32
18
16
18
19
GWE
BWE
BWd
ADV
ADSC
ADSP
CLK
CE0
CE1
CE2
BWc
BWb
BWa
OE
A[18:0]
ZZ
OE
FT
CLK
36/32
DATA [31:0]
Selection guide
-200
-166
-100
Units
Minimum cycle time
5
6
10
ns
Maximum clock frequency
200
166
100
MHz
Maximum pipelined clock access time
3.0
3.5
4.0
ns
Maximum operating current
400
350
250
mA
Maximum standby current
110
70
mA
Maximum CMOS standby current (DC)
30
mA
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相關代理商/技術參數 |
參數描述 |
|---|---|
| AS7C33512PFD36A-133TQC | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 512K x 32/36 pipelined burst synchronous SRAM |
| AS7C33512PFD36A-133TQCN | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 512K x 32/36 pipelined burst synchronous SRAM |
| AS7C33512PFD36A-133TQI | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 512K x 32/36 pipelined burst synchronous SRAM |
| AS7C33512PFD36A-133TQIN | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 512K x 32/36 pipelined burst synchronous SRAM |
| AS7C33512PFD36A-166TQC | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 512K x 32/36 pipelined burst synchronous SRAM |
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