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參數(shù)資料
| 型號： | AT1004S16 |
| 廠商： | POSEICO SPA |
| 英文描述： | PHASE CONTROL THYRISTOR |
| 中文描述： | 相位控制晶閘管 |
| 文件頁數(shù)： | 1/4頁 |
| 文件大小： | 170K |
| 代理商： | AT1004S16 |
PHASE CONTROL THYRISTOR
AT1004
Repetitive voltage up to
Mean on-state current
Surge current
1600
V
1545
A
24.6
kA
FINAL SPECIFICATION
feb 97 - ISSUE : 06
Symbol
Characteristic
Conditions
Tj
[°C]
Value
Unit
BLOCKING
V
RRM
Repetitive peak reverse voltage
125
1600
V
V
RSM
Non-repetitive peak reverse voltage
125
1700
V
V
DRM
Repetitive peak off-state voltage
125
1600
V
I
RRM
Repetitive peak reverse current
V=VRRM
125
50
mA
I
DRM
CONDUCTING
Repetitive peak off-state current
V=VDRM
125
50
mA
I
T (AV)
Mean on-state current
180° sin, 50 Hz, Th=55°C, double side cooled
1545
A
I
T (AV)
Mean on-state current
180° sin, 50 Hz, Tc=85°C, double side cooled
1255
A
I
TSM
Surge on-state current
sine wave, 10 ms
125
24.6
kA
I2 t
I2 t
without reverse voltage
3026 x1E3
A2s
V
T
On-state voltage
On-state current =
2900 A
25
1.63
V
V
T(TO)
Threshold voltage
125
0.92
V
r
T
On-state slope resistance
SWITCHING
125
0.216
mohm
di/dt
Critical rate of rise of on-state current, min.
From 75% VDRM up to 1650 A, gate 10V 5ohm
125
200
A/μs
dv/dt
Critical rate of rise of off-state voltage, min.
Linear ramp up to 70% of VDRM
125
500
V/μs
td
Gate controlled delay time, typical
VD=100V, gate source 25V, 10 ohm , tr=.5 μs
25
1.1
μs
tq
Circuit commutated turn-off time, typical
dV/dt = 20 V/μs linear up to 75% VDRM
250
μs
Q rr
Reverse recovery charge
di/dt=-20 A/μs, I= 1080 A
125
μC
I rr
Peak reverse recovery current
VR= 50 V
A
I
H
Holding current, typical
VD=5V, gate open circuit
25
300
mA
I
L
Latching current, typical
VD=5V, tp=30μs
25
700
mA
GATE
V
GT
Gate trigger voltage
VD=5V
25
3.5
V
I
GT
Gate trigger current
VD=5V
25
300
mA
V
GD
Non-trigger gate voltage, min.
VD=VDRM
125
0.25
V
V
FGM
Peak gate voltage (forward)
30
V
I
FGM
Peak gate current
10
A
V
RGM
Peak gate voltage (reverse)
5
V
P
GM
Peak gate power dissipation
Pulse width 100 μs
150
W
P
G
Average gate power dissipation
MOUNTING
2
W
R
th(j-h)
Thermal impedance, DC
Junction to heatsink, double side cooled
26
°C/kW
R
th(c-h)
Thermal impedance
Case to heatsink, double side cooled
6
°C/kW
T
j
F
Operating junction temperature
Mounting force
Mass
-30 / 125
18.0 / 20.0
500
°C
kN
g
ORDERING INFORMATION : AT1004 S 16
standard specification
VDRM&VRRM/100
POSEICO SPA
POwer SEmiconductors Italian COrporation
POSEICO
POSEICO SPA
Via N. Lorenzi 8, 16152 Genova - ITALY
Tel. ++ 39 010 6556234 - Fax ++ 39 010 6557519
Sales Office:
Tel. ++ 39 010 6556775 - Fax ++ 39 010 6442510
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