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參數資料
| 型號： | AT30TSE002B-MAH-T |
| 廠商： | Atmel |
| 文件頁數： | 16/36頁 |
| 文件大?。?/td> | 1184K |
| 描述： | SENSOR DGTL TEMP I2C/SMBUS 8WDFN |
| 標準包裝： | 5,000 |
| 系列： | * |
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16
Atmel AT30TSE002B [DATASHEET]
8711GSEEPR5/12
Table 11-6. Configuration Register Bit Description
Bit
Symbol
Description
15:11
RFU
Reserved for Future Use and must be zero.
10:9
HYSTENB
Hysteresis Enable:
00 = 0癈 Disable Hysteresis (default power-on condition)
01 = 1.5癈 Enable Hysteresis
10 = 3.0癈 Enable Hysteresis
11 = 6.0癈 Enable Hysteresis
The purpose of these bits is to control the hysteresis applied to the alarm trip point boundaries. The
above hysteresis applies to all limits when temperature drops below the user specified alarm trip
points.
Note:
Hysteresis applies to decreasing temperature only. Once ambient temperature is above
a given threshold, it must drop below the boundary limit minus hysteresis in order for a
comparator
EVENT to be cleared.
Example:
If these bits are set to 01 for 1.5癈 and the Upper Alarm Trip limit is set to 85癈, as
temperature rises above 85癈, bit 14 of temperature register will be set to a one. Bit 14
will remain set until the ambient temperature drops below the threshold (85癈) minus
the hysteresis value or 83.5癈.
Note:
Hysteresis is also applied to the
EVENT pin functionality.
When either of the Crit_Alarm
Trip or Alarm Window lock bits is set, this bit cannot be altered until unlocked.
8
SHTDWN
Shutdown Mode:
0 = Temperature sensor enabled for continuous conversion (power-on default).
1 = Temperature sensor disabled.
In shutdown mode, the temperature sensor is not active and will not generate interrupts or update
temperature data. The
EVENT pin is deasserted (not driven).
When either of the Crit_Alarm Trip or Alarm Window lock bits is set, this bit cannot be altered until
unlocked.
7
CRTALML
Crit_Alarm Trip Lock bit:
Locks the Critical Alarm Trip Register from being updated.
0 = Crit_Alarm Trip Register can be updated (power-on default).
1 = Crit_Alarm Trip Register is locked and cannot be updated.
Once set, it can be only be cleared to zero by internal POR which occurs when the device is powered
off and then powered on.
6
WINLOCK
Alarm Window Lock bit:
0 = Upper and Lower Alarm Trip Registers can be updated (Power-on default).
1 = Upper and Lower Alarm Trip Registers are locked and cannot be updated.
Once set, it can be only be cleared to zero by internal POR when device is powered off then powered
on.
5
EVTCLR
EVENT Clear: This bit is a write only bit and will read zero.
This bit can clear the
EVENT pin after it has been enabled and is self clearing.
0 = has no effect (power-on default).
1 = clears (releases) the active
EVENT pin in interrupt mode. This bit is ignored when in comparator
mode.
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