- 您現在的位置：買賣IC網 > PDF目錄366588 > AT655S28 (POSEICO SPA) PHASE CONTROL THYRISTOR PDF資料下載
參數資料
| 型號： | AT655S28 |
| 廠商： | POSEICO SPA |
| 英文描述： | PHASE CONTROL THYRISTOR |
| 中文描述： | 相位控制晶閘管 |
| 文件頁數： | 1/4頁 |
| 文件大小： | 44K |
| 代理商： | AT655S28 |
PHASE CONTROL THYRISTOR
AT655
Repetitive voltage up to
Mean on-state current
Surge current
2800
V
1545
A
30
kA
FINAL SPECIFICATION
feb 97 - ISSUE : 03
Symbol
Characteristic
Conditions
Tj
[°C]
Value
Unit
BLOCKING
V
RRM
Repetitive peak reverse voltage
125
2800
V
V
RSM
Non-repetitive peak reverse voltage
125
2900
V
V
DRM
Repetitive peak off-state voltage
125
2800
V
I
RRM
Repetitive peak reverse current
V=VRRM
125
70
mA
I
DRM
CONDUCTING
I
T (AV)
Repetitive peak off-state current
V=VDRM
125
70
mA
Mean on-state current
180° sin, 50 Hz, Th=55°C, double side cooled
1545
A
I
T (AV)
Mean on-state current
180° sin, 50 Hz, Tc=85°C, double side cooled
1330
A
I
TSM
Surge on-state current
sine wave, 10 ms
125
30
kA
I2 t
I2 t
without reverse voltage
4500 x1E3
A2s
V
T
On-state voltage
On-state current =
2900 A
25
1.8
V
V
T(TO)
Threshold voltage
125
1.05
V
r
T
On-state slope resistance
SWITCHING
di/dt
Critical rate of rise of on-state current, min.
125
0.290
mohm
From 75% VDRM up to 1730 A, gate 10V 5ohm 125
200
A/μs
dv/dt
Critical rate of rise of off-state voltage, min.
Linear ramp up to 70% of VDRM
125
500
V/μs
td
Gate controlled delay time, typical
VD=100V, gate source 10V, 10 ohm , tr=.5 μs
25
3
μs
tq
Circuit commutated turn-off time, typical
dV/dt = 20 V/μs linear up to 75% VDRM
320
μs
Q rr
Reverse recovery charge
di/dt=-20 A/μs, I= 1140 A
125
μC
I rr
Peak reverse recovery current
VR= 50 V
A
I
H
Holding current, typical
VD=5V, gate open circuit
25
300
mA
I
L
Latching current, typical
VD=5V, tp=30μs
25
700
mA
GATE
V
GT
Gate trigger voltage
VD=5V
25
3.5
V
I
GT
Gate trigger current
VD=5V
25
300
mA
V
GD
Non-trigger gate voltage, min.
VD=VDRM
125
0.25
V
V
FGM
Peak gate voltage (forward)
30
V
I
FGM
Peak gate current
10
A
V
RGM
Peak gate voltage (reverse)
5
V
P
GM
Peak gate power dissipation
Pulse width 100 μs
150
W
P
G
Average gate power dissipation
MOUNTING
R
th(j-h)
Thermal impedance, DC
2
W
Junction to heatsink, double side cooled
21
°C/kW
R
th(c-h)
Thermal impedance
Case to heatsink, double side cooled
6
°C/kW
T
j
F
Operating junction temperature
Mounting force
Mass
-30 / 125
22.0 / 24.5
520
°C
kN
g
ORDERING INFORMATION : AT655 S 28
standard specification
VDRM&VRRM/100
Via N. Lorenzi 8 - I 16152 GENOVA - ITALY
Tel. int. +39/(0)10 6556549 - (0)10 6556488
Fax Int. +39/(0)10 6442510
Tx 270318 ANSUSE I -
ANSALDO
Ansaldo Trasporti s.p.a.
Unita' Semiconduttori
相關PDF資料 |
PDF描述 |
|---|---|
| AT655 | PHASE CONTROL THYRISTOR |
| AT671 | PHASE CONTROL THYRISTOR |
| AT671S45 | PHASE CONTROL THYRISTOR |
| AT681 | PHASE CONTROL THYRISTOR |
| AT681S60 | PHASE CONTROL THYRISTOR |
相關代理商/技術參數 |
參數描述 |
|---|---|
| AT671 | 制造商:POSEICO 制造商全稱:POSEICO 功能描述:PHASE CONTROL THYRISTOR |
| AT671S45 | 制造商:POSEICO 制造商全稱:POSEICO 功能描述:PHASE CONTROL THYRISTOR |
| AT681 | 制造商:POSEICO 制造商全稱:POSEICO 功能描述:PHASE CONTROL THYRISTOR |
| AT68166F | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:Rad Hard 16 MegaBit 3.3V SRAM MultiChip Module |
| AT68166F_1 | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:Rad Hard 16 MegaBit 3.3V SRAM Multi-Chip Module |
發布緊急采購，3分鐘左右您將得到回復。