欧美成人免费电影,国产欧美一区二区三区精品酒店,精品国产a毛片,色网在线免费观看

參數(shù)資料
型號(hào)： ATT3020-100J44I
廠商： Electronic Theatre Controls, Inc.
元件分類： FPGA
英文描述： Field-Programmable Gate Arrays
中文描述： 現(xiàn)場(chǎng)可編程門陣列
文件頁(yè)數(shù)： 22/80頁(yè)
文件大小： 528K
代理商： ATT3020-100J44I
Data Sheet
February 1997
ATT3000 Series Field-Programmable Gate Arrays
22
Lucent Technologies Inc.
Configuration Modes
Master Mode
In master mode, the FPGA automatically loads configu-
ration data from an external memory device. There are
three master modes which use the internal timing
source to supply the configuration clock (CCLK) to time
the incoming data. Serial master mode uses serial con-
figuration data supplied to data-in (DIN) from a syn-
chronous serial source such as the serial configuration
PROM shown in Figure 21. Parallel master low and
master high modes automatically use parallel data sup-
plied to the D[7:0] pins in response to the 16-bit
address generated by the FPGA. Figure 22 shows an
example of the parallel master mode connections
required. The FPGA HEX starting address is 0000 and
increments for master low mode, and it is FFFF and
decrements for master high mode. These two modes
provide address compatibility with microprocessors
which begin execution from opposite ends of memory.
For master high or low, data bytes are read in parallel
by each read clock (
RCLK
) and internally serialized by
the configuration clock. As each data byte is read, the
least significant bit of the next byte, D0, becomes the
next bit in the internal serial configuration word. One
master mode FPGA can be used to interface the
configuration program-store, and pass additional
concatenated configuration data to additional FPGAs in
a serial daisy-chain fashion. CCLK is provided for the
slaved devices, and their serialized data is supplied
from DOUT to DIN, DOUT to DIN, etc.
Note: The serial configuration PROM supports automatic loading of configuration programs up to 36/64/128 Kbits. Multiple devices can be
cascaded to support additional FPGAs. An early DONE inhibits the data output one CCLK cycle before the FPGA I/O becomes active.
Figure 21. Master Serial Mode
5-3112(C)
DURING CONFIGURATION
THE 5 k
M2 PULL-DOWN
RESISTOR OVERCOMES THE
INTERNAL PULL-UP,
BUT IT ALLOWS M2 TO
BE USER I/O.
M0
M1
PWRDWN
+5 V
DOUT
M2
HDC
LDC
OTHER
I/O PINS
ATT3000
SERIES
FPGA
GENERAL-
PURPOSE
USER I/O
PINS
*
*
RESET
SYSTEM RESET
D/P
INIT
CCLK
DIN
CE
OE/RESET
CLK
DATA
ATT1700A
CEO
(HIGH RESETS THE ADDRESS POINTER)
CASCADED
ATT1700A
MEMORY
OPTIONAL
IDENTICAL SLAVE
FPGAs CONFIGURED
THE SAME
CE
OE/RESET
CLK
DATA
相關(guān)PDF資料
PDF描述
ATT3020-100J68I Field-Programmable Gate Arrays
ATT3020-100J84I Field-Programmable Gate Arrays
ATT3020-100M132I Field-Programmable Gate Arrays
ATT3020-100M44I Field-Programmable Gate Arrays
ATT3020-100M68I Field-Programmable Gate Arrays
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ATT3020-100J68I 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Gate Arrays
ATT3020-100J84I 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Gate Arrays
ATT3020-100M132I 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Gate Arrays
ATT3020-100M44I 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Gate Arrays
ATT3020100M68 制造商:Rochester Electronics LLC 功能描述:- Bulk
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*
主站蜘蛛池模板： 泾源县| 从江县| 上犹县| 信阳市| 兴城市| 松阳县| 宁国市| 虎林市| 阜城县| 年辖：市辖区| 夏津县| 萝北县| 成都市| 丰顺县| 大埔区| 南部县| 威海市| 旬阳县| 沂南县| 晋中市| 新平| 监利县| 塔城市| 耿马| 二连浩特市| 安阳县| 宜章县| 康马县| 防城港市| 二手房| 手游| 策勒县| 成安县| 新和县| 陇川县| 台北县| 丽江市| 鄄城县| 绥棱县| 龙门县| 四平市|