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| 型號： | ATT3020-125J44I |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | FPGA |
| 英文描述： | Field-Programmable Gate Arrays |
| 中文描述： | 現(xiàn)場可編程門陣列 |
| 文件頁數(shù)： | 29/80頁 |
| 文件大小： | 528K |
| 代理商： | ATT3020-125J44I |
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Data Sheet
February 1997
ATT3000 Series Field-Programmable Gate Arrays
Lucent Technologies Inc.
29
Performance
Device Performance
The high performance of the FPGA is due in part to the
manufacturing process, which is similar to that used for
high-speed CMOS static memories. Performance can
be measured in terms of minimum propagation times
for logic elements. The parameter which traditionally
describes the overall performance of a gate array is the
toggle frequency of a flip-flop. The configuration for
determining the toggle performance of the FPGA is
shown in Figure 26. The flip-flop output Q is fed back
through the combinatorial logic as Q to form the toggle
flip-flop.
Figure 26. Toggle Flip-Flop
FPGA performance is determined by the timing of
critical paths, including both the fixed timing for the
logic and storage elements in that path, and the timing
associated with the routing of the network. Examples
of internal worst-case timing are included in the
performance data to allow the user to make the best
use of the capabilities of the device. The
ORCA
Foundry Development System timing calculator or
ORCA
Foundry-generated simulation models should
be used to calculate worst-case paths by using actual
impedance and loading information.
Figure 27 shows a variety of elements which are
involved in determining system performance. Table 20
gives the parameter values for the different speed
grades. Actual measurement of internal timing is not
practical, and often only the sum of component
timing is relevant as in the case of input to output. The
relationship between input and output timing is arbi-
trary, and only the total determines performance.
Timing components of internal functions may be deter-
mined by the measurement of differences at the pins of
the package. A synchronous logic function which
involves a clock to block-output and a block-input to
clock setup is capable of higher-speed operation than a
logic configuration of two synchronous blocks with an
extra combinatorial block level between them. System
clock rates to 60% of the toggle frequency are practical
for logic in which an extra combinatorial level is located
between synchronized blocks. This allows implementa-
tion of functions of up to 25 variables. The use of the
wired-AND is also available for wide, high-speed
functions.
CLOCK
D Q
5-3117(F)
Figure 27. Examples of Primary Block Speed Factors
CLOCK
LOGIC
LOGIC
CLB
CLB
CLB
(K)
(K)
IOB
PAD
T
CKO
T
ILO
T
ICK
T
OP
CLOCK TO
OUTPUT
COMBINATORIAL
SETUP
IOB
T
PID
T
OKOP
T
CKO
PAD
5-3118(F)
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