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參數(shù)資料
型號(hào): ATT3020-125J44I
廠商: Electronic Theatre Controls, Inc.
元件分類: FPGA
英文描述: Field-Programmable Gate Arrays
中文描述: 現(xiàn)場(chǎng)可編程門陣列
文件頁(yè)數(shù): 56/80頁(yè)
文件大小: 528K
代理商: ATT3020-125J44I
Data Sheet
February 1997
ATT3000 Series Field-Programmable Gate Arrays
56
Lucent Technologies Inc.
Electrical Characteristics
(continued)
* These parameters are for clock pulses within an FPGA device. For externally applied clock, increase values by 20%.
Note: The CLB K to Q output delay (TCKO—#8) of any CLB, plus the shortest possible interconnect delay, is always longer than the data in
hold time requirement (TCKDI—#5) of any CLB on the same die.
Table 21. CLB Switching Characteristics (-3, -4, and -5)
Commercial: V
CC
= 5.0 V ± 5%; 0 °C
T
A
70 °C; Industrial: V
CC
= 5.0 ± 10%, –40 °C
T
A
+85 °C.
Description
Symbol
-5
-4
-3
Unit
Min
Max
4.1
Min
Max
3.3
Min
Max
2.7
Combinatorial Delay
Sequential Delay
Clock K to Outputs x or y
Clock K to Outputs x or y when Q Returned
Through Function Generators F or G to
Drives x or y
Setup Time
Logic Variables
Data In
Enable Clock
Reset Direct Active
Hold Time
Logic Variables
Data In
Enable Clock
Clock
High Time*
Low Time*
Flip-Flop Toggle Rate*
Reset Direct (rd)
rd Width
Delay from rd to Outputs x, y
Master Reset (MR)
MR Width
Delay from MR to Outputs x, y
1
T
ILO
ns
8
T
CKO
T
QLO
3.1
6.3
2.5
5.2
2.1
4.3
ns
ns
2
4
6
T
ICK
T
DICK
T
ECCK
T
RDCK
3.1
2.0
3.8
1.0
2.5
1.6
3.2
1.0
2.1
1.4
2.7
1.0
ns
ns
ns
ns
3
5
7
T
CKI
T
CKDI
T
CKEC
0
1.2
1.0
0
1.0
0.8
0
0.9
0.7
ns
ns
ns
11
12
T
CH
T
CL
F
CLK
2.4
2.4
190
2.0
2.0
230
1.6
1.6
270
ns
ns
MHz
13
9
T
RPW
T
RIO
3.8
4.4
3.2
3.7
2.7
3.1
ns
ns
T
MRW
T
MRQ
18.0
17.0
15.0
14.0
13.0
12.0
ns
ns
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