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參數(shù)資料
| 型號： | ATT3020-50T44I |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | FPGA |
| 英文描述： | Field-Programmable Gate Arrays |
| 中文描述： | 現(xiàn)場可編程門陣列 |
| 文件頁數(shù)： | 10/80頁 |
| 文件大小： | 528K |
| 代理商： | ATT3020-50T44I |
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Data Sheet
February 1997
ATT3000 Series Field-Programmable Gate Arrays
10
Lucent Technologies Inc.
Programmable Interconnect
(continued)
General-Purpose Interconnect
General-purpose interconnect, as shown in Figure 9,
consists of a grid of five horizontal and five vertical
metal segments located between the rows and col-
umns of logic and IOBs. Each segment is the height or
width of a logic block. Switching matrices join the ends
of these segments and allow programmed interconnec-
tions between the metal grid segments of adjoining
rows and columns. The switches of an unprogrammed
device are all nonconducting. The connections through
the switch matrix may be established by automatic or
interactive routing by selecting the desired pairs of
matrix pins to be connected or disconnected. The
legitimate switching matrix combinations for each pin
are indicated in Figure 10.
Special buffers within the general interconnect areas
provide periodic signal isolation and restoration for
improved performance of lengthy nets. The intercon-
nect buffers are available to propagate signals in either
direction on a given general interconnect segment.
These bidirectional (bidi) buffers are found adjacent to
the switching matrices, above and to the right. The
other PIPs adjacent to the matrices are accessed to or
from long lines. The development system automatically
defines the buffer direction based on the location of the
interconnection network source. The delay calculator in
the
ORCA
Foundry Development System automatically
calculates and displays the block, interconnect, and
buffer delays for any paths selected. Generation of the
simulation netlist with a worst-case delay model is also
provided by the development system.
Some of the interconnect PIPs are directional, as
indicated below:
I
ND is a nondirectional interconnection.
I
D:H->V is a PIP which drives from a horizontal to a
vertical line.
I
D:V->H is a PIP which drives from a vertical to a
horizontal line.
I
D:C->T is a T-PIP which drives from a cross of a
T to the tail.
I
D:CW is a corner PIP which drives in the clockwise
direction.
I
P0 indicates the PIP is nonconducting; P1 is on.
Figure 9. FPGA General-Purpose Interconnect
Figure 10. Switch Matrix Interconnection Options
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