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參數(shù)資料
| 型號(hào)： | LC5768MC-5F484C |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | PLD |
| 英文描述： | 3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD⑩ Family |
| 中文描述： | EE PLD, 6 ns, PBGA484 |
| 封裝： | FPBGA-484 |
| 文件頁數(shù)： | 1/92頁 |
| 文件大小： | 378K |
| 代理商： | LC5768MC-5F484C |
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www.latticesemi.com
1
ispXPLD
3.3V, 2.5V and 1.8V In-System Programmable
eXpanded Programmable Logic Device XPLD Family
5000MX Family
August 2004
Data Sheet
TM
2004 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The speci
fi
cations and information herein are subject to change without notice.
Features
Flexible Multi-Function Block (MFB)
Architecture
SuperWIDE logic (up to 136 inputs)
Arithmetic capability
Single- or Dual-port SRAM
FIFO
Ternary CAM
sysCLOCK PLL Timing Control
Multiply and divide between 1 and 32
Clock shifting capability
External feedback capability
sysIO Interfaces
LVCMOS 1.8, 2.5, 3.3V
– Programmable impedance
– Hot-socketing
– Flexible bus-maintenance (Pull-up, pull-
down, bus-keeper, or none)
– Open drain operation
SSTL 2, 3 (I & II)
HSTL (I, III, IV)
PCI 3.3
GTL+
LVDS
LVPECL
LVTTL
■
■
■
■
Expanded In-System Programmability (ispXP)
Instant-on capability
Single chip convenience
In-System Programmable via IEEE 1532
Interface
In
fi
nitely recon
fi
gurable via IEEE 1532 or
sysCONFIG microprocessor interface
Design security
High Speed Operation
4.0ns pin-to-pin delays, 300MHz f
Deterministic timing
Low Power Consumption
Typical static power: 20 to 50mA (1.8V),
30 to 60mA (2.5/3.3V)
1.8V core for low dynamic power
Easy System Integration
3.3V (5000MV), 2.5V (5000MB) and 1.8V
(5000MC) power supply operation
5V tolerant I/O for LVCMOS 3.3 and LVTTL
interfaces
IEEE 1149.1 interface for boundary scan testing
sysIO quick con
fi
guration
Density migration
Multiple density and package options
PQFP and
fi
ne pitch BGA packaging
Lead-free package options
■
MAX
■
■
Table 1. ispXPLD 5000MX Family Selection Guide
ispXPLD 5256MX
256
8
128K
48K
2
4.0ns
2.2ns
2.8ns
300MHz
75K
141
ispXPLD 5512MX
512
16
256K
96K
2
4.5ns
2.8ns
3.0ns
275MHz
150K
149/193/253
208 PQFP
256 fpBGA
484 fpBGA
ispXPLD 5768MX ispXPLD 51024MX
768
24
384K
144K
2
5.0ns
2.8ns
3.2ns
250MHz
225K
193/317
Macrocells
Multi-Function Blocks
Maximum RAM Bits
Maximum CAM Bits
sysCLOCK PLLs
t
PD
(Propagation Delay)
t
S
(Register Set-up Time)
t
CO
(Register Clock to Out Time)
f
MAX
(Maximum Operating Frequency)
System Gates
I/Os
Packages
1,024
32
512K
192K
2
5.2ns
3.0ns
3.7ns
250MHz
300K
317/381
256 fpBGA
256 fpBGA
484 fpBGA
484 fpBGA
672 fpBGA
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LC5768MC-5F484I | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD⑩ Family |
| LC5768MC-5F672C | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD⑩ Family |
| LC5768MC-5F672I | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD⑩ Family |
| LC5768MC-5FN208C | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD⑩ Family |
| LC5768MC-5FN208I | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD⑩ Family |
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