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參數資料
| 型號： | C9530CT |
| 英文描述： | ST7262 - LOW SPEED USB 8-BIT MCU WITH 3 ENDPOINTS, FLASH OR ROM MEMORY, LVD, WDG, 10-BIT ADC, 2 TIMERS, SCI, SPI |
| 中文描述： | CPU系統時鐘發生器|的CMOS | TSSOP封裝| 48PIN |塑料 |
| 文件頁數： | 1/14頁 |
| 文件大小： | 180K |
| 代理商： | C9530CT |
PCIX I/O System Clock Generator With EMI Control Features
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07033 Rev. **
5/1/2000
Page 1 of 14
APPROVED PRODUCT
C9530
Product Features
Dedicated clock buffer power pins for reduced
noise, crosstalk and jitter
Buffer XIN Reference clock output
Input clock frequency 33.3 MHz
Reference may be a clock or a crystal
Output frequencies of 33.3, 66.6, 100 and 133.3
MHz selectable (PCIX requirements)
Output grouped in two banks of 5 clocks each.
SMBus clock control interface for individual clock
disabling, SSCG control and individual bank
frequency selection
Output clock duty cycle is 50% (
±
5%)
<250 pS skew between output clocks within a bank
Output jitter <250 pSec. (175pSec with all outputs
at the same frequency)
Spread Spectrum feature for reduced EMI
OE pins for separate output bank enable control
and testability
48 Pin SSOP and TSSOP package
Block Diagram
Test Mode Logic Table
INPUT PINS
OEA
SA1
OEB
SB1
HIGH
LOW
HIGH
LOW
HIGH
HIGH
HIGH
HIGH
LOW
X
Note
: A and B banks have separate frequency select
and output enable controls. XIN is the frequency of the
clock on the device’s XIN pin. OEA or OEB will tristate
REF.
OUTPUT PINS
CLKA(0:4)
CLKB(0:4)
XIN
2 * XIN
3 * XIN
4 * XIN
Tri-State
SA0
SB0
LOW
HIGH
LOW
HIGH
X
REF
XIN
XIN
XIN
XIN
Tri-State
Pin Configuration
XIN
CLKB4
OEB
BGOOD#
REF
CLKB3
CLKB2
CLKB1
CLKB0
CLKA3
CLKA4
OEA
CLKA2
CLKA1
CLKA0
/N
SSCG#
SSCG
Logic
/N
1
0
1
0
XOUT
I
2
C
Control
Logic
SCLK
IA(0:2)
SA(0,1)
SB(0,1)
AGOOD#
SDATA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
XIN
VDD
XOUT
VSS
SA0
SA1
VSS
CLKA0
CLKA1
VDDA
CLKA2
VSS
VDDA
CLKA4
VSS
AGOOD#
VSS
IA0
IA1
IA2
AVDD
OEA
OEB
VSS
SSCG#
VSS
AVDD
BGOOD#
AVDD
CLKB4
VSS
VDDB
CLKB3
VSS
VDDB
CLKB2
CLKB1
VSS
CLKB0
SB1
SB0
VDD
VSS
VDD
SCLK
SDATA
C
REF
41
42
43
44
45
46
47
48
CLKA3
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相關代理商/技術參數 |
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| C9531CY | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:CPU SYSTEM CLOCK GENERATOR|SSOP|28PIN|PLASTIC |
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