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參數資料
| 型號： | CA3252E |
| 廠商： | INTERSIL CORP |
| 元件分類： | 外設及接口 |
| 英文描述： | Quad Gated Non-Inverting Power Driver |
| 中文描述： | 1 A 4 CHANNEL, AND GATE BASED PRPHL DRVR, PDIP16 |
| 封裝： | PLASTIC, MS-001BB, DIP-16 |
| 文件頁數： | 1/6頁 |
| 文件大小： | 53K |
| 代理商： | CA3252E |
1
March 1998
CA3252
Quad Gated Non-Inverting Power Driver
Features
Four 600mA Non-Inverting Power Output Drivers
50V and 1A Maximum Rated Power Output Drivers
V
CE(SUS)
Capability . . . . . . . . . . . . . . . . . . . . . . . . .35V
Inputs Compatible With TTL or 5V CMOS Logic
Suitable For Resistive, Lamp or Inductive Loads
Inductive Clamps on Each Output
High Dissipation Power-Frame Package
Operating Temperature Ranges . . . . . . -40
o
C to 105
o
C
Applications
Solenoids
Relays
Lamps
Steppers
Small Motors
Displays
System Applications
Automotive
Appliances
Industrial Controls
Robotics
Description
The CA3252 is used to interface low-level logic to high cur-
rent loads. Each Power Driver has four inverting switches
consisting of an inverting logic input stage and an inverting
low-side driver output stage. All inputs are 5V TTL/CMOS
logic compatible and have a common Enable input. On-chip
steering diodes are connected from each output (in pairs) to
the CLAMP pins (in pairs) which may be used in conjunction
with external zener diodes to protect the IC against over-volt-
age transients that result from inductive load switching. The
CA3252 may be used in a variety of automotive and indus-
trial control applications to drive relays, solenoids, lamps and
small motors.
To allow for maximum heat transfer from the chip, all ground
pins on the DIP and SOIC packages are directly connected
to the mounting pad of the chip. Integral heat spreading lead
frames directly connect the bond pad and ground leads for
good heat dissipation. In a typical application, the package is
mounted on a copper PC Board. By increasing copper
ground area on the PC Board, more heat is conducted away
from the ground leads. The junction-to-ambient thermal
resistances may be reduced to less than 40
o
C/W with
approximately two square inches of copper area.
Pinouts
CA3252E
(PDIP)
TOP VIEW
CA3252M
(SOIC)
TOP VIEW
Ordering Information
PART
NUMBER
TEMP. (
o
C)
PACKAGE
PKG. NO.
CA3252E
-40 to 105
16 Ld PDIP
E16.3
CA3252M
-40 to 105
20 Ld SOIC
M20.3
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
OUT A
CLAMP AB
OUT B
GND
GND
OUT C
CLAMP CD
OUT D
IN A
IN B
ENABLE
GND
GND
V
CC
IN C
IN D
11
12
13
14
15
16
17
18
20
19
10
9
8
7
6
5
4
3
2
1
CLAMP AB
NC
NC
OUT B
GND
GND
NC
OUT C
NC
CLAMP CD
OUT A
INB
ENABLE
GND
IN A
GND
V
CC
IN C
IN D
OUT D
File Number
1542.2
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
|
Copyright
Intersil Corporation 1999
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