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參數(shù)資料
| 型號： | CD40104BMS |
| 廠商： | Intersil Corporation |
| 英文描述： | CMOS 4-Bit Bidirectional Universal Shift Register(CMOS ４位雙向通用移位寄存器) |
| 中文描述： | 的CMOS 4位雙向通用移位寄存器（的CMOS 4位雙向通用移位寄存器） |
| 文件頁數(shù)： | 1/10頁 |
| 文件大小： | 129K |
| 代理商： | CD40104BMS |
7-1307
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright Intersil Corporation 1999
CD40104BMS,
CD40194BMS
CMOS 4-Bit Bidirectional
Universal Shift Register
Pinouts
CD40104BMS
TOP VIEW
CD40194BMS
TOP VIEW
Functional Diagrams
CD40104BMS
CD40194BMS
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
OUTPUT ENABLE
SHIFT RIGHT IN
D0
D1
D2
D3
VSS
SHIFT LEVEL IN
VDD
Q1
Q2
Q3
CLOCK
SELECT 1
SELECT 0
Q0
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
RESET
SHIFT RIGHT IN
D0
D1
D2
D3
VSS
SHIFT LEVEL IN
VDD
Q1
Q2
Q3
CLOCK
SELECT 1
SELECT 0
Q0
3
4
5
6
7
2
9
10
D0
D1
D2
D3
CLOCK
S0
S1
SHIFT LEFT IN
SHIFT RIGHT IN
MODE SELECT
11
15
14
13
12
Q0
Q1
Q2
Q3
OUTPUT ENABLE
1
VDD = 16
VSS = 8
3
4
5
6
7
2
9
10
D0
D1
D2
D3
CLOCK
S0
S1
SHIFT LEFT IN
SHIFT RIGHT IN
MODE SELECT
11
15
14
13
12
Q0
Q1
Q2
Q3
RESET
1
VDD = 16
VSS = 8
Features
High Voltage Type (20V Rating)
Medium Speed fCL = 12MHz (typ.) at VDD = 10V
Fully Static Operation
Synchronous Parallel or Serial Operation
Three State Outputs (CD40104BMS)
Asynchronous Master Reset (CD40194BMS)
5V, 10V and 15V Parametric Ratings
Standardized Symmetrical Output Characteristics
Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
‘B’ Series CMOS Devices”
Applications
Arithmetic Unit Bus Registers
Serial/Parallel Conversions
General Purpose Register for Bus Organized Systems
General Purpose Registers
Description
The CD40104BMS is a universal shift register featuring parallel
inputs, parallel outputs, SHIFT RIGHT and SHIFT LEFT serial
inputs, and a high impedance third output state allowing the device
to be used in bus organized systems.
In the parallel load mode (S0 and S1 are high), data is loaded into
the associated flip-flop and appears at the output after the positive
transition of the CLOCK input. During loading, serial data flow is
inhibited. Shift right and shift left are accomplished synchronously
on the positive clock edge with serial data entered at the SHIFT
RIGHT and SHIFT LEFT serial inputs, respectively. Clearing the
register is accomplished by setting both mode controls low and
clocking the register. When the output enable input is low, all outputs
assume the high impedance state.
The CD40194BMS is a universal shift register featuring parallel inputs,
parallel outputs SHIFT RIGHT and SHIFT LEFT serial inputs, and a
direct overriding clear input. In the parallel load mode (S0 and S1 are
high), data is loaded into the associated flip-flop and appears at the out-
put after the positive transition of the CLOCK input. During loading,
serial data flow is inhibited. Shift right and shift left are accomplished
synchronously on the positive clock edge with data entered at the
SHIFT RIGHT and SHIFT LEFT serial inputs, respectively. Clocking of
the register is inhibited when both mode control inputs are low. When
low, the RESET input resets all stages and forces all outputs low. The
CD40194BMS is similar to industry types 340194 and MC40194.
The CD40104BMS and CD40194BMS series types are supplied in
these 16 lead outline packages
Braze Seal DIP
Frit Seal DIP
Ceramic Flatpack
* CD40104B Only
*HNX,
*H1L,
H6W
CD40194B Only
H4W
HIF
File Number
3352
December 1992
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