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參數資料
| 型號： | CD4015BMS |
| 廠商： | Intersil Corporation |
| 英文描述： | CMOS Dual 4-Stage Static Shift Register With Serial Input/Parallel Output(串行輸入并行輸出的CMOS 雙四級靜態移位寄存器) |
| 中文描述： | CMOS雙4級靜態移位寄存器在串行輸入/并行輸出（串行輸入并行輸出的的CMOS雙四級靜態移位寄存器） |
| 文件頁數： | 1/8頁 |
| 文件大小： | 118K |
| 代理商： | CD4015BMS |
7-89
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright Intersil Corporation 1999
CD4015BMS
CMOS Dual 4-Stage Static Shift Register
With Serial Input/Parallel Output
Pinout
CD4015BMS
TOP VIEW
Functional Diagram
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
CLOCK B
Q4B
Q3A
Q2A
Q1A
RESET A
VSS
DATA A
VDD
RESET B
Q1B
Q2B
Q3B
Q4A
CLOCK A
DATA B
DATA A
CLOCK A
RESET A
DATA B
CLOCK B
RESET B
Q1A
Q2A
Q3A
Q4A
Q1B
Q2B
Q3B
Q4B
VSS
VDD
16
7
9
6
15
1
14
5
4
3
10
13
12
11
2
8
4
STAGE
4
STAGE
Features
High-Voltage Type (20V Rating)
Medium Speed Operation 12MHz (typ.) Clock Rate at
VDD - VSS = 10V
Fully Static Operation
8 Master-Slave Flip-Flops Plus Input and Output Buffering
100% Tested For Quiescent Current at 20V
5V, 10V and 15V Parametric Ratings
Standardized Symmetrical Output Characteristics
Maximum Input Current of 1
μ
A at 18V Over Full Pack-
age-Temperature Range; 100nA at 18V and 25
o
C
Noise Margin (Full Package-Temperature Range) =
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
‘B’ Series CMOS Devices”
Applications
Serial-Input/Parallel-Output Data Queueing
Serial to Parallel Data Conversion
General-Purpose Register
Description
CD4015BMS consists of two identical, independent, 4-stage
serial-input/parallel output registers. Each register has inde-
pendent CLOCK and RESET inputs as well as a single serial
DATA input. “Q” outputs are available from each of the four
stages on both registers. All register stages are D type, mas-
ter-slave flip-flops. The logic level present at the DATA input
is transferred into the first register stage and shifted over one
stage at each positive-going clock transition. Resetting of all
stages is accomplished by a high level on the reset line.
Register expansion to 8 stages using one CD4015BMS
package, or to more than 8 stages using additional
CD4015BMS’s is possible.
The CD4015BMS is supplied in these 16 lead outline pack-
ages:
Braze Seal DIP
H4X
Frit Seal DIP
H1F
Ceramic Flatpack
H6W
December 1992
File Number
3295
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相關代理商/技術參數 |
參數描述 |
|---|---|
| CD4015BMT | 功能描述:計數器移位寄存器 CMOS Dual 4-Stage Static Shift Reg RoHS:否 制造商:Texas Instruments 計數器類型: 計數順序:Serial to Serial/Parallel 電路數量:1 封裝 / 箱體:SOIC-20 Wide 邏輯系列: 邏輯類型: 輸入線路數量:1 輸出類型:Open Drain 傳播延遲時間:650 ns 最大工作溫度:+ 125 C 最小工作溫度:- 40 C 封裝:Reel |
| CD4015BMTE4 | 功能描述:計數器移位寄存器 CMOS Dual 4-Stage Static Shift Reg RoHS:否 制造商:Texas Instruments 計數器類型: 計數順序:Serial to Serial/Parallel 電路數量:1 封裝 / 箱體:SOIC-20 Wide 邏輯系列: 邏輯類型: 輸入線路數量:1 輸出類型:Open Drain 傳播延遲時間:650 ns 最大工作溫度:+ 125 C 最小工作溫度:- 40 C 封裝:Reel |
| CD4015BMTG4 | 功能描述:計數器移位寄存器 CMOS Dual 4-Stage Static Shift Reg RoHS:否 制造商:Texas Instruments 計數器類型: 計數順序:Serial to Serial/Parallel 電路數量:1 封裝 / 箱體:SOIC-20 Wide 邏輯系列: 邏輯類型: 輸入線路數量:1 輸出類型:Open Drain 傳播延遲時間:650 ns 最大工作溫度:+ 125 C 最小工作溫度:- 40 C 封裝:Reel |
| CD4015BNS | 制造商:Rochester Electronics LLC 功能描述: 制造商:Texas Instruments 功能描述: |
| CD4015BNSR | 功能描述:計數器移位寄存器 CMOS Dual 4-Stage Static Shift Reg RoHS:否 制造商:Texas Instruments 計數器類型: 計數順序:Serial to Serial/Parallel 電路數量:1 封裝 / 箱體:SOIC-20 Wide 邏輯系列: 邏輯類型: 輸入線路數量:1 輸出類型:Open Drain 傳播延遲時間:650 ns 最大工作溫度:+ 125 C 最小工作溫度:- 40 C 封裝:Reel |
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