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參數資料
| 型號： | CD4021 |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | 8-Stage Static Shift Register |
| 中文描述： | 8級靜態移位寄存器 |
| 文件頁數： | 1/9頁 |
| 文件大小： | 93K |
| 代理商： | CD4021 |
7-80
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright Intersil Corporation 1999
CD4014BMS,
CD4021BMS
CMOS 8-Stage Static Shift Registers
Description
CD4014BMS -Synchronous Parallel or Serial Input/Serial Output
CD4021BMS -Asynchronous Parallel Input or Synchronous
Serial Input/Serial Output
CD4014BMS and CD4021BMS series types are 8-stage paral-
lel- or serial-input/serial output registers having common CLOCK
and PARALLEL/SERIAL CONTROL inputs, a single SERIAL
data input, and individual parallel “JAM” inputs to each register
stage. Each register stage is a D-type, master-slave flip-flop. In
addition to an output from stage 8, “Q” outputs are also available
from stages 6 and 7. Parallel as well as serial entry is made into
the register synchronously with the positive clock line transition in
the CD4014BMS. In the CD4021BMS serial entry is synchro-
nous with the clock but parallel entry is asynchronous. In both
types, entry is controlled by the PARALLEL/SERIAL CONTROL
input. When the PARALLEL/SERIAL CONTROL input is low,
data is serially shifted into the 8-stage register synchronously
with the positive transition of the clock line. When the PARALLEL/
SERIAL CONTROL input is high, data is jammed into the 8-
stage register via the parallel input lines and synchronous with
the positive transition of the clock line. In the CD4021BMS, the
CLOCK input of the internal stage is “forced” when asynchro-
nous parallel entry is made. Register expansion using multiple
packages is permitted.
The CD4014BMS and CD4021BMS are supplied in these 16
lead outline packages:
Braze Seal DIP
Frit Seal DIP
Ceramic Flatpack
H4T
H1F
H6W
Features
High Voltage Types (20V Rating)
Medium Speed Operation 12MHz (Typ.) Clock Rate at
VDD-VSS = 10V
Fully Static Operation
8 Master-Slave Flip-Flops Plus Output Buffering and
Control Gating
100% Tested for Quiescent Current at 20V
Maximum Input Current of 1
μ
A at 18V Over Full Pack-
age Temperature Range; 100nA at 18V and +25
o
C
Noise Margin (Full Package Temperature Range)
1V at VDD = 5V
2V at VDD = 10V
2.5V at VDD = 15V
Standardized Symmetrical Output Characteristics
5V, 10V and 15V Parametric Ratings
Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
`B' Series CMOS Devices
Applications:
Parallel Input/Serial Output Data Queueing
Parallel to Serial Data Conversion
General Purpose Register
File Number
3294
December 1992
Functional Diagram
14 15
13
1
4
5
6
7
16
1 2 3 4 5 6 7 8
VDD
PAR. IN
VSS
12
3
2
11
10
9
Q6
Q7
Q8
PARALLEL/SERIAL
CONTROL
SERIAL IN
CLOCK
B
O
8
Pinout
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
PI-8
Q6
Q8
PI-4
PI-3
PI-2
VSS
PI-1
VDD
PI-6
PI-5
Q7
SERIAL IN
CLOCK
PARALLEL/SERIAL
CONTROL
PI-7
相關PDF資料 |
PDF描述 |
|---|---|
| CD4021BC | 8-Stage Static Shift Register |
| CD4021BCM | 8-Stage Static Shift Register |
| CD4021BCN | 8-Stage Static Shift Register |
| CD4022BC | Decade Counter/Divider with 10 Decoded Outputs, Divide-by-8 Counter/Divider with 8 Decoded Outputs |
| CD4022BCJ | Decade Counter/Divider with 10 Decoded Outputs, Divide-by-8 Counter/Divider with 8 Decoded Outputs |
相關代理商/技術參數 |
參數描述 |
|---|---|
| CD4021AD3 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CD4021AE | 制造商:Semiconductors 功能描述: 制造商:RCA 功能描述:Shift Register, 16 Pin, Plastic, DIP |
| CD4021AF/3 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CD4021AFX | 制造商:RCA 功能描述:Shift Register, 16 Pin, Ceramic, DIP |
| CD4021AR1022 | 制造商:Harris Corporation 功能描述: |
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