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參數(shù)資料
| 型號： | CD4095BMS |
| 廠商： | Intersil Corporation |
| 英文描述： | CMOS J-K Master-Slave Flip-Flops(CMOS J-K 主從觸發(fā)器) |
| 中文描述： | 的CMOS JK主從觸發(fā)器（的CMOS JK主從觸發(fā)器） |
| 文件頁數(shù)： | 1/10頁 |
| 文件大小： | 101K |
| 代理商： | CD4095BMS |
7-1094
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright Intersil Corporation 1999
CD4095BMS
CD4096BMS
CMOS Gated J-K
Master-Slave Flip-Flops
Features
Set-Reset Capability
High Voltage Types (20V Rating)
CD4095BMS Non-Inverting J and K Inputs
CD4096BMS Inverting and Non-Inverting J and K
Inputs
16MHz Toggle Rate (Typ.) at VDD - VSS = 10V
Gated Inputs
100% Tested for Quiescent Current at 20V
5V, 10V and 15V Parametric Ratings
Standardized Symmetrical Output Characteristics
Maximum Input Current of 1
μ
A at 18V Over Full Pack-
age Temperature Range; 100nA at 18V and +25
o
C
Noise Margin (Over Full Package/Temperature Range)
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
Meets all requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
‘B’ Series CMOS Devices”
Applications
Registers
Counters
Control Circuits
Description
CD4095BMS and CD4096BMS are J-K Master-Slave Flip-
Flops featuring separate AND gating of multiple J and K
inputs. The gated J-K inputs control transfer of information
into the master section during clocked operation. Information
on the J-K inputs is transferred to the Q and Q outputs on
the positive edge of the clock pulse. SET and RESET inputs
(active high) are provided for asynchronous operation.
The CD4095BMS and CD4096BMS are supplied in these 14
lead outline packages:
Braze Seal DIP
Frit Seal DIP
H4Q
H1A
File Number
3331
Pinouts
CD4095BMS
TOP VIEW
CD4096BMS
TOP VIEW
Functional Diagrams
CD4095BMS
CD4096BMS
NC
RESET
J1
J2
J3
Q
VSS
VDD
SET
CLOCK
K1
K2
K3
Q
1
2
3
4
5
6
7
14
13
12
11
10
9
8
NC
RESET
J1
J2
J3
Q
VSS
VDD
SET
CLOCK
K1
K2
K3
Q
1
2
3
4
5
6
7
14
13
12
11
10
9
8
NC = NO CONNECTION
VDD = 14
VSS = 7
NC = 1
SET
J2
J3
13
3
4
5
J1
K2
K3
11
10
9
K1
12
CLOCK
S
J
Q
CL
K
R
Q
Q
Q
RESET
2
6
8
VDD = 14
VSS = 7
NC = 1
SET
J2
J3
13
3
4
5
J1
K2
K3
11
10
9
K1
12
CLOCK
S
J
Q
CL
K
R
Q
Q
Q
RESET
2
6
8
December 1992
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