
7-1188
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright Intersil Corporation 1999
CD4514BMS
CD4515BMS
CMOS 4-Bit
Latch/4-to-16 Line Decoders
File Number
3195
December 1992
Pinout
CD4514BMS, CD4515BMS
TOP VIEW
Functional Diagram
1
2
3
4
5
6
7
8
9
10
11
12
STROBE
DATA 1
DATA 2
S7
S6
S5
S4
S3
S2
S1
S0
VSS
16
17
18
19
20
21
22
23
24
15
14
13
VDD
DATA 4
DATA 3
S10
S11
S9
S15
S12
S13
INHIBIT
S8
S14
INHIBIT
23
11
S0
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
S11
S12
S13
S14
S15
9
10
8
7
6
5
4
18
17
20
19
14
13
16
15
4 TO 16
DECODER
VDD = 24
VSS = 12
LATCH
A
B
C
D
DATA 1
DATA 2
DATA 3
DATA 4
2
3
21
22
STROBE
1
Features
High-Voltage Types (20-Volt Rating)
CD4514BMS Output “High” on Select
CD4515BMS Output “Low” on Select
Strobed Input Latch
Inhibit Control
100% Tested for Quiescent Current at 20V
Maximum Input Current of 1
μ
A at 18V Over Full Pack-
age Temperature Range; 100nA at 18V and 25
o
C
Noise Margin (Full Package-Temperature Range):
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
5V, 10V, and 15V Parametric Ratings
Standardized, Symmetrical Output Characteristics
Meets all Requirements of JEDEC Tentative Standard
No. 13B, "Standard Specifications for Description of
‘B’ Series CMOS Devices"
Applications
Digital Multiplexing
Address Decoding
Hexadecimal/BCD Decoding
Program-counter Decoding
Control Decoder
Description
CD4514BMS and CD4515BMS consist of a 4-bit strobed
latch and a 4-to-16-line decoder. The latches hold the last
input data presented prior to the strobe transition from 1 to 0.
Inhibit control allows all outputs to be placed at
0(CD4514BMS) or 1(CD4515BMS) regardless of the state of
the data or strobe inputs.
The decode truth table indicates all combinations of data
inputs and appropriate selected outputs.
These devices are similar to industry types MC14514 and
MC14515.
The CD4514BMS and CD4515BMS are supplied in these 24
lead outline packages:
Braze Seal DIP
Frit Seal DIP
Ceramic Flatpack
H4V
H1Z
H4P