- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄379830 > CDC2516DGG (Texas Instruments, Inc.) 3.3-V PHASE-LOCK LOOP CLOCK DRIVER PDF資料下載
參數(shù)資料
| 型號： | CDC2516DGG |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 3.3-V PHASE-LOCK LOOP CLOCK DRIVER |
| 中文描述： | 3.3 - V相位鎖相環(huán)時鐘驅(qū)動器 |
| 文件頁數(shù)： | 1/11頁 |
| 文件大小： | 160K |
| 代理商： | CDC2516DGG |
CDC2516
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS579A – OCTOBER 1996 – REVISED JANUARY 1998
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Phase-Lock Loop Clock Distribution for
Synchronous DRAM Applications
Distributes One Clock Input to Four Banks
of Four Outputs
Separate Output Enable for Each Output
Bank
External Feedback Pin (FBIN) Is Used to
Synchronize the Outputs to the Clock Input
On-Chip Series-Damping Resistors
No External RC Network Required
Operates at 3.3-V V
CC
Packaged in Plastic 48-Pin Thin Shrink
Small-Outline Package
description
The CDC2516 is a high-performance, low-skew,
low-jitter, phase-lock loop (PLL) clock driver. It
uses a PLL to precisely align, in both frequency
and phase, the feedback output (FBOUT) to the
clock (CLK) input signal. It is specifically designed
for use with synchronous DRAMs. The CDC2516
operates at 3.3-V V
CC
and provides integrated
series-damping resistors that make it ideal for
driving point-to-point loads.
Four banks of four outputs provide 16 low-skew,
low-jitter copies of the input clock. Output signal
duty cycles are adjusted to 50 percent,
independent of the duty cycle at the input clock.
Each bank of outputs can be enabled or disabled
separately via the 1G, 2G, 3G, and 4G control
inputs. When the G inputs are high, the outputs
switch in phase and frequency with CLK; when the
G inputs are low, the outputs are disabled to the
logic-low state.
Unlike many products containing PLLs, the CDC2516 does not require external RC networks. The loop filter
for the PLL is included on-chip, minimizing component count, board space, and cost.
Because it is based on PLL circuitry, the CDC2516 requires a stabilization time to achieve phase lock of the
feedback signal to the reference signal. This stabilization time is required following power up and application
of a fixed-frequency, fixed-phase signal at CLK, as well as following any changes to the PLL reference or
feedback signals. The PLL may be bypassed for test purposes by strapping AV
CC
to ground.
The CDC2516 is characterized for operation from 0
°
C to 70
°
C.
Copyright
1998, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
V
CC
1Y0
1Y1
GND
GND
1Y2
1Y3
V
CC
1G
GND
AV
CC
CLK
AGND
AGND
GND
2G
V
CC
2Y0
2Y1
GND
GND
2Y2
2Y3
V
CC
V
CC
4Y0
4Y1
GND
GND
4Y2
4Y3
V
CC
4G
GND
AV
CC
FBIN
AGND
FBOUT
GND
3G
V
CC
3Y0
3Y1
GND
GND
3Y2
3Y3
V
CC
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
DGG PACKAGE
(TOP VIEW)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CDC2587 | Octal Divided -by-2 Circuit/Clock Driver(3.3V鎖相環(huán)時鐘驅(qū)動器(三態(tài)輸出)) |
| CDC303 | "1-To-8 |
| CDC3244 | 3.3-V ABT Octal Clock Driver with 3 State Output(3.3VABT八時鐘驅(qū)動器(三態(tài)輸出)) |
| CDC328ADB | ECONOLINE: RSZ/P - 1kVDC |
| CDC330 | Clock Driver with 3 state Output(時鐘驅(qū)動器(三態(tài)輸出)) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CDC2516DGGR | 功能描述:時鐘驅(qū)動器及分配 3.3VPhase Lock Loop ClockDrvr RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| CDC2516DGGRG4 | 功能描述:時鐘驅(qū)動器及分配 3.3V Ph-Lock Loop Clock Driver RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| CDC2536 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS |
| CDC2536DB | 功能描述:時鐘驅(qū)動器及分配 3.3V PLL Clock Drvr RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| CDC2536DBG4 | 功能描述:時鐘驅(qū)動器及分配 3.3V PLL Clock Drvr RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。