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參數資料
| 型號： | CDC857-3DGG |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 2.5-/3.3-V PHASE-LOCK LOOP CLOCK DRIVERS |
| 中文描述： | 2.5-/3.3-V鎖相環時鐘驅動器 |
| 文件頁數： | 1/12頁 |
| 文件大?。?/td> | 157K |
| 代理商： | CDC857-3DGG |
CDC857-2, CDC857-3
2.5-/3.3-V PHASE-LOCK LOOP CLOCK DRIVERS
SCAS627A – SEPTEMBER 1999 – DECEMBER 1999
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Phase-Lock Loop Clock Distribution for
Double Data Rate Synchronous DRAM
Applications
Distributes One Differential Clock Input to
Ten Differential Outputs
External Feedback Pins (FBIN, FBIN) Are
Used to Synchronize the Outputs to the
Clock Input
Operates at V
CC
= 2.5 V and AV
CC
= 3.3 V
Packaged in Plastic 48-Pin (DGG) Thin
Shrink Small-Outline Package (TSSOP)
Spread Spectrum Clocking Tracking
Capability to Reduce EMI
description
The CDC857-2 and CDC857-3 are high-perfor-
mance, low-skew, low-jitter, phase-lock loop
(PLL) clock driver. They use a PLL to precisely
align, in both frequency and phase, the feedback
(FBOUT) output to the clock (CLK) input signal.
The CDC857-3 operates at 3.3 V (PLL) and 2.5 V
(output buffer). The CDC857-2 operates at
2.5 V (PLL and output buffer).
One bank of ten inverting and noninverting
outputs provide ten low-skew, low-jitter copies of
CLK. Output signal duty cycles are adjusted to
50%, independent of the duty cycle at CLK.
All outputs can be enabled or disabled via a single output enable input. When the G input is high, the outputs
switch in phase and frequency with CLK; when the G input is low, the outputs are disabled to high impedance
state (3-state).
Unlike many products containing PLLs, the CDC857 does not require external RC networks. The loop filter for
the PLL is included on-chip, minimizing component count, board space, and cost.
Because it is based on PLL circuity, the CDC857 requires a stabilization time to achieve phase lock of the
feedback signal to the reference signal. This stabilization time is required following power up and application
of a fixed-frequency, fixed-phase signal at CLK, as well as following any changes to the PLL reference or
feedback signals. The PLL can be bypassed for test purposes by strapping AV
CC
to ground. If AV
CC
is at GND
and V
CC
= ON, 2 falling edges on G cause the PLL to run with FBOUT being enabled and all other outputs being
disabled, after AV
CC
ramps up to its specified V
CC
value, with G being kept low. The CDC857 is characterized
for operation from 0
°
C to 85
°
C.
Copyright
1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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GND
Y0
Y0
V
CC
Y1
Y1
GND
GND
Y2
Y2
V
CC
V
CC
CLK
CLK
V
CC
AV
CC
AGND
GND
Y3
Y3
V
CC
Y4
Y4
GND
GND
Y5
Y5
V
CC
Y6
Y6
GND
GND
Y7
Y7
V
CC
G
FBIN
FBIN
V
CC
FBOUT
FBOUT
GND
Y8
Y8
V
CC
Y9
Y9
GND
DGG PACKAGE
(TOP VIEW)
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相關代理商/技術參數 |
參數描述 |
|---|---|
| CDC857-3DGGG4 | 功能描述:鎖相環 - PLL Phase-Lock Loop Clock Drivers RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| CDC857-3DGGR | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CDC906 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:PROGRAMMABLE 3-PLL CLOCK SYNTHESIZER / MULTIPLIER / DIVIDER |
| CDC906PW | 功能描述:時鐘合成器/抖動清除器 Custom Prog 3-PLL Clock RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| CDC906PWG4 | 功能描述:時鐘合成器/抖動清除器 Custom Prog 3-PLL Clock RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
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