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參數資料
| 型號： | CDCU877ZQL |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 1.8V PHASE LOCK LOOP CLOCK DRIVER |
| 中文描述： | 1.8鎖相環時鐘驅動器 |
| 文件頁數： | 1/17頁 |
| 文件大?。?/td> | 410K |
| 代理商： | CDCU877ZQL |
SCAS688A JUNE 2003 REVISED JANUARY 2004
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
1.8-V Phase Lock Loop Clock Driver for
Double
Data Rate (DDR II) Applications
Spread Spectrum Clock Compatible
Operating Frequency: 10 MHz to 400 MHz
Low Current Consumption: <135 mA
Low Jitter (Cycle-Cycle):
±
30 ps
Low Output Skew: 35 ps
Low Period Jitter:
±
20 ps
Low Dynamic Phase Offset::
±
15 ps
Low Static Phase Offset::
±
50 ps
Distributes One Differential Clock Input to
Ten Differential Outputs
52-Ball
μ
BGA (MicroStar Junior
BGA,
0,65-mm pitch) and 40-Pin MLF
External Feedback Pins (FBIN, FBIN) are
Used to Synchronize the Outputs to the
Input Clocks
Single-Ended Input and Single-Ended
Output Modes
Meets or Exceeds JESD82-8 PLL Standard
for PC2-3200/4300
Fail-Safe Inputs
description
The CDCU877 is a high-performance, low-jitter, low-skew, zero-delay buffer that distributes a differential clock input
pair (CK, CK) to ten differential pairs of clock outputs (Yn, Yn) and to one differential pair of feedback clock outputs
(FBOUT, FBOUT). The clock outputs are controlled by the input clocks (CK, CK), the feedback clocks (FBIN, FBIN),
the LVCMOS control pins (OE, OS), and the analog power input (AV
DD
). When OE is low, the clock outputs, except
FBOUT/FBOUT, are disabled while the internal PLL continues to maintain its locked-in frequency. OS (output select)
is a program pin that must be tied to GND or V
DD
. When OS is high, OE functions as previously described. When
OS and OE are both low, OE has no affect on Y7/Y7, they are free running. When AV
DD
is grounded, the PLL is turned
off and bypassed for test purposes.
When both clock inputs (CK, CK) are logic low, the device enters in a low power mode. An input logic detection circuit
on the differential inputs, independent from input buffers, detects the logic low level and performs in a low power state
where all outputs, the feedback, and the PLL are off. When the clock inputs transition from being logic low to being
differential signals, the PLL turns back on, the inputs and the outputs are enabled, and the PLL obtains phase lock
between the feedback clock pair (FBIN, FBIN) and the clock input pair (CK, CK) within the specified stabilization time.
The CDCU877 is able to track spread spectrum clocking (SSC) for reduced EMI. This device operates from –40
°
C
to 85
°
C.
AVAILABLE OPTIONS
TA
52-Ball BGA
40-Pin MLF
40
°
C to 85
°
C
CDCU877ZQL
(Pb-Free)
CDCU877RTB
40
°
C to 85
°
C
CDCU877AZQL
(Pb-Free)
CDCU877ARTB
40
°
C to 85
°
C
40
°
C to 85
°
C
CDCU877GQL
CDCU877AGQL
Copyright
2004, Texas Instruments Incorporated
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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
MicroStar Junior is a trademark of Texas Instruments.
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相關代理商/技術參數 |
參數描述 |
|---|---|
| CDCU877ZQLR | 功能描述:時鐘驅動器及分配 1.8v PLL Clock Driver RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| CDCU877ZQLT | 功能描述:時鐘驅動器及分配 1.8v PLL Clock Driver RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| CDCUA877 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:1.8-V PHASE LOCK LOOP CLOCK DRIVER |
| CDCUA877_1 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:1.8-V PHASE LOCK LOOP CLOCK DRIVER |
| CDCUA877ZQL | 制造商:TI 制造商全稱:Texas Instruments 功能描述:1.8-V PHASE LOCK LOOP CLOCK DRIVER |
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