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參數(shù)資料
| 型號： | CDP1823C |
| 廠商： | Intersil Corporation |
| 英文描述： | High-Reliability CMOS 128-Word x 8-Bit Static RAM |
| 中文描述： | 高可靠性的CMOS 128字× 8位靜態(tài)存儲器 |
| 文件頁數(shù)： | 1/6頁 |
| 文件大小： | 28K |
| 代理商： | CDP1823C |
6-31
March 1997
CDP1823C/3
High-Reliability CMOS
128-Word x 8-Bit Static RAM
Features
For Applications in Aerospace, Military, and Critical
Industrial Equipment
Compatible with CDP1800-Series Microprocessors at
Maximum Speed
Interfaces with CDP1800-Series Microprocessors
without Additional Components
Fast Access Time
At V
DD
= 5V, +25
o
C . . . . . . . . . . . . . . . . . . . . . . . .275ns
Single Voltage Supply
Common Data Inputs and Outputs
Multiple Chip Select Inputs to Simplify Memory
System Expansion
High Noise Immunity . . . . . . . . . . . . . . . . . . 30% of V
DD
Memory Retention for Standby Battery Voltage Down
to 2V at 25
o
C
Latch-Up-Free Transient Radiation Tolerance
Description
The CDP1823C/3 is a 128 word x 8-bit CMOS/SOS static
random access memory. It is compatible with the CDP1802,
CDP1804, CDP1805, and CDP1806 microprocessors, and
will interface directly without additional components. The
CDP1823C has a recommended operating voltage range of
4V to 6.5V.
The CDP1823C memory has 8 common data input and data
output terminals for direct connection to a bidirectional data
bus and is operated from a single voltage supply. Five chip
select inputs are provided to simplify memory system
expansion. In order to enable the CDP1823C, the chip select
inputs CS2, CS3, and CS5 require a low input signal, and
the chip select inputs CS1 and CS4 require a high input
signal.
The MRD signal enables all 8 output drivers when in the low
state and should be in a high state during a write cycle.
After valid data appear at the output, the address inputs may
be changed immediately. Output data will be valid until either
the MRD signal goes high, the device is deselected, or t
AA
(access time) after address changes.
Pinout
CDP1823C/3
(SBDIP)
TOP VIEW
Ordering Information
PACKAGE
TEMP. RANGE
-55
o
C to +125
o
C CDP1823CD3
PART NUMBER
(5V)
PKG. NO.
SBDIP
D24.6
1
2
3
4
5
6
7
8
9
10
11
12
BUS 0
BUS 1
BUS 2
BUS 3
BUS 4
BUS 5
BUS 6
BUS 7
CS1
CS2
CS3
V
SS
16
17
18
19
20
21
22
23
24
15
14
13
V
DD
A0
A1
A2
A3
A4
A6
MRD
CS5
CS4
A5
MWR
File Number
2982.1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
|
Copyright
Intersil Corporation 1999
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CDP1823CD3 | High-Reliability CMOS 128-Word x 8-Bit Static RAM |
| CDP1823 | 128-Word x 8-Bit LSI Static RAM |
| CDP1823CD | 128-Word x 8-Bit LSI Static RAM |
| CDP1823CDX | 128-Word x 8-Bit LSI Static RAM |
| CDP1823CE | 128-Word x 8-Bit LSI Static RAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CDP1823C/3 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:High-Reliability CMOS 128-Word x 8-Bit Static RAM |
| CDP1823CD | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:128-Word x 8-Bit LSI Static RAM |
| CDP1823CD/B | 制造商:Rochester Electronics LLC 功能描述: |
| CDP1823CD3 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:High-Reliability CMOS 128-Word x 8-Bit Static RAM |
| CDP1823CDX | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:128-Word x 8-Bit LSI Static RAM |
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