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參數(shù)資料
| 型號： | CG7C324-A15JC |
| 英文描述： | UV-Erasable/OTP PLD |
| 中文描述： | UV-Erasable/OTP可編程邏輯器件 |
| 文件頁數(shù)： | 1/13頁 |
| 文件大小： | 326K |
| 代理商： | CG7C324-A15JC |
Reprogrammable Asynchronous
CMOS Logic Device
PLDC20RA10
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
December 1987 - Revised March 26, 1997
0RA10
Features
Advanced-user programmable macrocell
CMOS EPROM technology for reprogrammability
Up to 20 input terms
10 programmable I/O macrocells
Output macrocell programmable as combinatorial or
asynchronous D-type registered output
Product-term control of register clock, reset and set and
output enable
Register preload and power-up reset
Four data product terms per output macrocell
Fast
—Commercial
t
PD
= 15 ns
t
CO
= 15 ns
t
SU
= 7 ns
—Military
t
PD
= 20 ns
t
CO
= 20 ns
t
SU
= 10 ns
Low power
—I
CC
max - 80 mA (Commercial)
—I
CC
max = 85 mA (Military)
High reliability
—Proven EPROM technology
—>2001V input protection
—100% programming and functional testing
Windowed DIP, windowed LCC, DIP, LCC, PLCC avail-
abl
e
Functional Description
The Cypress PLDC20RA10 is a high-performance, sec-
ond-generation programmable logic device employing a flexi-
ble macrocell structure that allows any individual output to be
configured independently as a combinatorial output or as a
fully asynchronous D-type registered output.
The Cypress PLDC20RA10 provides lower-power operation
with superior speed performance than functionally equivalent
bipolar devices through the use of high-performance 0.8-mi-
cron CMOS manufacturing technology.
The PLDC20RA10 is packaged in a 24 pin 300-mil molded DIP
a 300-mil windowed cerDIP and a 28-lead square leadless
chip carrier, providing up to 20 inputs and 10 outputs. When
the windowed device is exposed to UV light, the 20RA10 is
erased and can then be reprogrammed.
Logic Block Diagram
4
9
8
7
6
5
4
3
2
1
10
15
16
17
18
19
20
21
22
23
24
I
I
I
I
I
I
I
I
4
4
4
4
4
4
4
V
CC
11
12
13
14
I
V
SS
OE
4
4
I
I/O
9
I/O
8
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
I/O
2
I/O
1
I/O
0
4
4
4
4
4
4
4
4
4
4
MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL
9
8
7
6
5
4
3
2
1
0
PL
RA10–1
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CG7C324-A20JC | UV-Erasable/OTP PLD |
| CG7C324-A30HC | UV-Erasable/OTP PLD |
| CG7C324-A30JC | UV-Erasable/OTP PLD |
| PLDC20RA10-30HC | UV-Erasable/OTP PLD |
| PLDC20RA10-30WC | UV-Erasable/OTP PLD |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CG7C324-A20HC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:UV-Erasable/OTP PLD |
| CG7C324-A20JC | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Reprogrammable Asynchronous CMOS Logic Device |
| CG7C324A20JCT | 制造商:CYPRESS 功能描述:NEW |
| CG7C324-A20JCT | 制造商:Cypress Semiconductor 功能描述:OT PLD, 20 ns, PQCC28 |
| CG7C324-A30HC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:UV-Erasable/OTP PLD |
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