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參數(shù)資料
| 型號(hào)： | CGS701ATV |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | Commercial, Industrial Low Skew PLL 1 to 8 CMOS Clock Driver |
| 中文描述： | 701 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC28 |
| 封裝： | PLASTIC, LCC-28 |
| 文件頁(yè)數(shù)： | 1/10頁(yè) |
| 文件大小： | 162K |
| 代理商： | CGS701ATV |
TL/F/11920
C
C
December 1995
CGS701AV
Commercial Low Skew PLL 1 to 8 CMOS Clock Driver
CGS701ATV
Industrial Low Skew PLL 1 to 8 CMOS Clock Driver
General Description
CGS701A is an off the shelf clock driver specifically de-
signed for today’s high speed designs. It provides low skew
outputs which are produced at different frequencies from
three fixed input references. The XTALIN input pin is de-
signed to be driven from a 25 MHz–40 MHz crystal oscilla-
tor.
The PLL, using a charge pump and an internal loop filter,
multiplies this input frequency to create a maximum output
frequency of four times the input.
The device includes a TRI-STATE
é
control pin to disable
the outputs. This feature allows for low frequency functional
testing and debugging.
Also included, is an EXTSEL pin to allow testing the chip via
an external source. The EXTSEL pin, once set to high, caus-
es the External-ClockDMUX to change its input from the
output of the VCO and Counter to the external clock signal
provided via SKWTST input pin.
(continued)
Features
Y
Guaranteed:
400 ps pin-to-pin skew (t
OSHL
and t
OSLH
) on 1X
outputs.
Y
Pentium
é
and PowerPC
TM
compatible
Y
g
300 ps propagation delay
Y
Output buffer of eight drivers for large fanout
Y
25 MHz–160 MHz output frequency range
Y
Outputs operating at 4X, 2X, 1X of the reference fre-
quency for multifrequency bus applications
Y
Selectable output frequency
Y
Internal loop filter to reduce noise and jitter
Y
Separate analog and digital V
CC
and ground pins
Y
Low frequency test mode by disabling the PLL
Y
Implemented on National’s Core CMOS process
Y
Symmetric output current drive:
a
30/
b
30 mA I
OL
/I
OH
Y
Industrial temperature of
b
40
§
C to
a
85
§
C
Y
28-pin PLCC for optimum skew performance
Y
Guaranteed 2k volts ESD protection
Connection Diagram
Pin Assignment for PLCC
TL/F/11920–1
Pin Description
PLCC Package
Pin
Name
Description
1
2
3
4
5
6
7
8
9
V
CC
FBK IN
CLK4
V
CC
XTALIN
GND
FBK OUT
V
CC
CLK1Dl
GND
CLK1D2
TRI-STATE
SKWTST
CLK1D3
GND
CLK1D4
V
CC
SKWSEL
GNDA
V
CCA
EXTSEL
GND
CLK1D5
V
CC
CLK1D0
CLK1SEL
GND
CLK2
Digital V
CC
Feedback Input Pin
4X Clock Output
Digital V
CC
Crystal Oscillator Input
Digital Ground
Feedback Output Pin
Digital V
CC
1X Clock Output
Digital Ground
1X Clock Output
Output TRI-STATE Control
Skew Testing Pin
1X Clock Output
Digital Ground
1X Clock Output
Digital V
CC
Skew Test Selector Pin
Analog Ground
Analog V
CC
External Clock MUX Selector
Digital Ground
1X Clock Output
Digital V
CC
1X Clock Output
CLK1 Multiplier Selector
Digital Ground
2X Clock Output
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Pentium
é
is a registered trademark of Intel Corporation.
PowerPC
TM
is a trademark of International Business Machines Corporation.
TRI-STATE
é
is a registered trademark of National Semiconductor Corporation.
C
1996 National Semiconductor Corporation
RRD-B30M106/Printed in U. S. A.
http://www.national.com
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