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參數資料
| 型號： | CH7202 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | MPEG to TV Encoder with 8-bit Input |
| 中文描述： | 電視的MPEG編碼器8位輸入 |
| 文件頁數： | 1/16頁 |
| 文件大小： | 110K |
| 代理商： | CH7202 |
201-0000-030 Rev 2.0, 6/2/99
1
CH7202
CHRONTEL
MPEG to TV Encoder with 8-bit Input
Features
Outputs NTSC, PAL (B,D,G,H,I) and PAL-M (NTSC-
J or PAL-60 available as options)
8-bit YCrCb (4:2:2) input format
Master or slave mode operation
Triple 9-bit DAC for composite and S-video output
27 MHz DAC operating frequency eliminates
the need for 1/sinc(x) correction filter
Low-jitter phase-locked loop circuitry operates using a
low-cost 14.31818 MHz crystal
40.5 or 33.9 MHz video decoder clock output
16.934 or 11.289 MHz audio decoder clock output
13.5 MHz and 27 MHz video pixel clock outputs
Internal 4.6 MHz (max) luminance and 1.3 MHz
chrominance filters
Sub-carrier genlocked to HSYNC* and VSYNC*
Sleep mode
CMOS technology in 44-pin PLCC
5V single-supply operation
Description
The CH7202 video encoder integrates a dual PLL clock
generator and a digital NTSC/PAL video encoder. By
generating all essential clock signals for MPEG
playback, and converting digital video inputs to either
NTSC or PAL video signals, the CH7202 is an essential
component of any low-cost solution for video-CD
playback machines.
The CH7202 dual PLL clock synthesizer generates all
clocks and timing signals from a 14.31818 MHz
reference crystal (see application note 19 “Tuning
Clock Outputs” for selection and tuning of the 14.31818
MHz crystal). The CH7202 will accept HSYNC*,
VSYNC*, and 2XPCLK clock inputs during slave
mode operation. Timing signals from the PLLs can be
used to generate the horizontal and vertical sync signals
which enable operating the CH7202 in master mode.
The fully digital video encoder is pin-programmable to
generate either a 525-line NTSC or a 625-line PAL
compatible video signal. It also features a logic
selectable sleep mode which turns the encoder off while
leaving both PLL’s running.
Figure 1: Functional Block Diagram
U
FILTER
V
FILTER
DAC
DAC
DAC
Σ
Σ
X
M
U
X
M
U
X
M
U
X
Y
FILTER
B LA NKIN G
COLO R-B URST
CO NTRO L
BLAN KING
H ,V SYNC
GEN ERATO R
X
SIN + COSINE
GENERATOR
ACLK
2XPCLK
Y
CVBS
C
YC[7:0],
IREF
RSET
AVDD
VDD
AGND
GND
XI
XO/FIN
MOD0
MOD1
FS
LINEAR
INTERPOLATO R
INTERFACE
PLL1
STATE
MACHINE
OSC
PLL2
PCLK
DCLK
HSYNC*
VSYNC*
8
CbSWAP
YCSWAP
M/S*
1/2
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相關代理商/技術參數 |
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| CH7203 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MPEG to TV Encoder with 16-bit Input |
| CH7203-V | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MPEG to TV Encoder with 16-bit Input |
| CH720S-40PT | 制造商:CHENMKO 制造商全稱:Chenmko Enterprise Co. Ltd. 功能描述:SCHOTTKY BARRIER DIODE VOLTAGE 40 Volts CURRENT 0.04 Ampere |
| CH721C276MA80A8 | 制造商:AVX Corporation 功能描述: |
| CH721UPT | 制造商:CHENMKO 制造商全稱:Chenmko Enterprise Co. Ltd. 功能描述:SCHOTTKY BARRIER DIODE VOLTAGE 40 Volts CURRENT 0.2 Ampere |
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