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參數資料
| 型號： | CY2081SL-XXX |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | XO, clock |
| 英文描述： | Three-PLL General-Purpose EPROM-Programmable Clock Generator |
| 中文描述： | 80 MHz, OTHER CLOCK GENERATOR, PDSO8 |
| 封裝： | 0.150 INCH, SOIC-8 |
| 文件頁數： | 1/6頁 |
| 文件大?。?/td> | 111K |
| 代理商： | CY2081SL-XXX |
Three-PLL General-Purpose
EPROM-Programmable Clock Generator
CY2081
Cypress Semiconductor Corporation
Document #: 38-07136 Rev. **
3901 North First Street
San Jose
CA 95134
Revised September 26, 2001
408-943-2600
1
Features
Factory-EPROM configurable for quick availability and
prototyping
General purpose clock synthesizer for all applications
– such as modems, disk drives, CD-ROM drives, Video
CD players, games, set-top boxes, data/telecommuni-
cations, etc.
Three independent configurable clock outputs
Outputs ranging from 500 kHz to 100 MHz (5V) and up
to 80 MHz for 3.3V operation
Configurable output control pin (pin 8) can be used as
an output enable, power-down, suspend or select line.
Phase-locked loop oscillator input derived from exter-
nal crystal (10 MHz to 25 MHz) or external reference
clock (1 MHz to 30 MHz)
3.3V or 5V operation (factory configured)
8-pin 150-mil packaging achieves minimum footprint
for space-critical applications
Sophisticated internal loop filter requires no external
components or manufacturing tweaks as commonly re-
quired with external filters
Functional Description
The CY2081 is a general-purpose clock synthesizer designed
for use in applications such as modems, disk drives, CD-ROM
drives, Video CD players, games, set-top boxes and data/tele-
communications. This devices offers three configurable clock
outputs in an 8-pin 150-mil SOIC package and can be config-
ured to operate off either a 3.3V or 5V power supply. The
on-chip reference oscillator is designed for 10 MHz to 25 MHz
crystals. Alternatively, a reference clock between 1 MHz and
30 MHz can be used.
The CY2081 also features an output control pin (pin 8), which
can be configured as an output enable, power down, frequen-
cy select, or suspend input. This gives the user the ability to
three-state the output, power down the device, change the
CLKA output frequency during operation, or suspend any of
the outputs. Asserting the PD input will result in all the PLLs
and the outputs being shut down. The PLLs will have to re-lock
when the PD input is deasserted.
The CY2081 outputs three clocks: CLKA, CLKB, and CLKC,
whose frequencies can possess any value within the specified
range. Additionally, the reference frequency can be obtained
on any output. Custom configurations with user-defined fea-
tures and frequencies can be obtained by filling out the custom
configuration form located at the back of this data sheet and
contacting your local Cypress representative.
The CY2081 can replace multiple Metal Can Oscillators
(MCO) in a synchronous system, providing cost and board
space savings to manufacturers. Hence, this device is ideally
suited for applications that require multiple, accurate, and sta-
ble clocks synthesized from low-cost generators in small pack-
ages. A hard disk drive is an example of such an application.
In this case, CLKA drives the PLL in the Read Controller, while
CLKB and CLKC drive the MCU and associated sequencers.
Consider using the CY2291, CY2292, or CY2907 for applica-
tions that require more than three output clocks.
Pin Configuration
SOIC
Top View
1
2
3
4
5
8
7
6
CLKA
GND
XTALIN
XTALOUT
V
DD
CLKC
CLKB
Logic Block Diagram
XTALOUT
XTALIN
Reference
Oscillator
PLL 1
CLKA
CLKB
CLKC
EPROM-
Configurable
Multiplexer
and Divide
Logic
PLL 2
PLL 3
OE/PD/FS/SUSPEND
OE/PD/FS/SUSPEND
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