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參數(shù)資料
| 型號： | CY241V08-11 |
| 英文描述： | Clocks and Buffers |
| 中文描述： | 時鐘和緩沖器 |
| 文件頁數(shù)： | 1/7頁 |
| 文件大小： | 92K |
| 代理商： | CY241V08-11 |
MPEG Clock Generator with VCXO
CY2410
Cypress Semiconductor Corporation
Document #: 38-07317 Rev. *D
3901 North First Street
San Jose
,
CA 95134
408-943-2600
Revised December 11, 2003
Features
Integrated phase-locked loop (PLL)
Low-jitter, high-accuracy outputs
VCXO with analog adjust
3.3V operation
Compatible with MK3727 (–1, –4, –5, –6, –7)
Benefits
Highest-performance PLL tailored for multimedia applica-
tions
Meets critical timing requirements in complex system
designs
Large ±150-ppm range, better linearity
Application compatibility for a wide variety of designs
Enables design compatibility
Advanced Features
Serial programming interface (CY2410-3 only)
Lower drive strength settings (CY2410-4, -6)
Matches nonlinear MK3727A VCXO control curve (-5, -6)
Matches nonlinear MK3727C VCXO control curve (-7)
Benefits
Digital VCXO control
Electromagnetic interference (EMI) reduction for standards
compliance
Second source for existing designs
Part
Number
CY2410–1
Outputs
1
Input Frequency Range
13.5-MHz pullable crystal input per
Cypress specification
13.5-MHz pullable crystal input per
Cypress specification
13.5-MHz pullable crystal input per
Cypress specification
13.5-MHz pullable crystal input per
Cypress specification
13.5-MHz pullable crystal input per
Cypress specification
13.5-MHz pullable crystal input per
Cypress specification
Output
Frequencies
1 copy of 27 MHz linear
VCXO Control
Curve
Other Features
Compatible with MK3727
CY2410–3
1
1 copy of 27 MHz linear
Serial programming interface
CY2410–4
1
1 copy of 27 MHz linear
Same as CY2410–1 except
lower drive strength settings
Matches MK3727A nonlinear
VCXO Control Curve
Same as CY2410–5 except
lower drive strength
Matches MK3727C nonlinear
VCXO control curve
CY2410–5
1
1 copy of 27 MHz nonlinear
CY2410–6
1
1 copy of 27 MHz nonlinear
CY2410–7
1
1 copy of 27 MHz nonlinear
CY2410–1,–4,–5,–6,–7 Logic Block Diagram
13.5 XIN
XOUT
OUTPUT
DIVIDERS
PLL
OSC
VCXO
Q
P
VCO
VDD
VSS
Φ
27 MHz
13.5 XIN
XOUT
OUTPUT
DIVIDERS
PLL
OSC
Q
P
VCO
VDD
VSS
Φ
27 MHz
CY2410–3 Logic Block Diagram
Serial
Programming
Interface
SCLK
SDAT
Digital VCXO
8-pin SOIC
CY2410–1,–4,–5,–6,–7
1
2
3
4
XOUT
XIN
VDD
VCXO
VSS
27 MHz
NC or VSS
NC or VDD
5
6
7
8
8-pin SOIC
CY2410–3
1
2
3
4
XOUT
XIN
VDD
SDAT
VSS
SCLK
NC or VSS
27 MHz
5
6
7
8
Pin Configurations
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相關(guān)代理商/技術(shù)參數(shù) |
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| CY241V08-41 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Clocks and Buffers |
| CY241V08A-01 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:MPEG Clock Generator with VCXO |
| CY241V08A-02 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:MPEG Clock Generator with VCXO |
| CY241V08A-04 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:MPEG Clock Generator with VCXO |
| CY241V08A-05 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:MPEG Clock Generator with VCXO |
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