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參數資料
| 型號： | CY24233 |
| 英文描述： | Clocks and Buffers |
| 中文描述： | 時鐘和緩沖器 |
| 文件頁數： | 1/15頁 |
| 文件大小： | 150K |
| 代理商： | CY24233 |
Spread Spectrum Frequency Timing Generator
CY24239
Cypress Semiconductor Corporation
Document #: 38-07038 Rev. **
3901 North First Street
San Jose
CA 95134
408-943-2600
Revised May 18, 2001
39
Features
Maximized EMI Suppression using Cypress’s Spread
Spectrum Technology
–1.2% and –2.4% Spread Spectrum support
Three copies of CPU output
Seven copies of PCI output
One 48-MHz output for USB / One 24-MHz for SIO
Two buffered reference outputs
Two IOAPIC outputs
Seventeen SDRAM outputs provide support for
4 DIMMs
SMBus interface for programming
Power management control inputs
Key Specifications
CPU Cycle-to-Cycle Jitter:.......................................... 250 ps
CPU to CPU Output Skew:......................................... 350 ps
PCI to PCI Output Skew: ............................................ 500 ps
SDRAMIN to SDRAM0:16 Delay:..........................3.7 ns typ.
V
DDQ3
: ....................................................................
3.3V±5%
Table 1. Mode Input Table
Mode
0
1
Intel is a registered trademark of Intel Corporation.
Pin 3
PCI_STOP#
REF0
Table 2. Pin Selectable Frequency
Input Address
CPU_F,
CPU1:2
(MHz)
91.66
75.0
100.0
83.3
66.6
105.0
110.0
133.3
91.66
75.0
100.0
83.3
91.66
75.0
100.0
83.3
PCI_F,
PCI0:5
(MHz)
30.5
25.0
33.3
27.76
33.3
26.3
27.5
33.3
30.5
25.0
33.3
27.76
30.5
25.0
33.3
27.76
Spread
Spec-
trum
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
–
1.2%
–
1.2%
–
1.2%
–
1.2%
–
2.4%
–
2.4%
–
2.4%
–
2.4%
FS3
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
FS2
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
FS1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
FS0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Block Diagram
Pin Configuration
Note:
1.
Internal pull-up resistors should not be relied upon for setting I/O
pins HIGH. Pin function with parentheses determined by MODE pin
resistor strapping. Unlike other I/O pins, input FS3 has an internal
pull-down resistor.
[1]
VDDQ3
REF0/(PCI_STOP#)
VDDQ3
IOAPIC_F
CPU_F
CPU1
CPU2
PCI_F/MODE
PCI0/FS3
XTAL
OSC
PLL Ref Freq
PLL 1
X2
X1
REF1/FS2
VDDQ3
Stop
Clock
Stop
Clock
Control
PCI1
PCI2
PCI3
PCI5
VDDQ3
48MHz/FS1
24MHz/FS0
VDDQ3
PLL2
÷
2,3,4
VDDQ3
CLK_STOP#
IOAPIC0
PCI4
SMBus
Logic
SDATA
SCLK
I/O Pin
Control
SDRAM0:16
SDRAMIN
17
Stop
Stop
Clock
Control
VDDQ3
REF1/FS2
REF0/(PCI_STOP#)
GND
X1
X2
VDDQ3
PCI_F/MODE
PCI0/FS3
GND
PCI1
PCI2
PCI3
PCI4
VDDQ3
PCI5
SDRAMIN
SDRAM11
SDRAM10
VDDQ3
SDRAM9
SDRAM8
GND
SDRAM15
SDRAM14
C
VDDQ3
IOAPIC0
IOAPIC_F
GND
CPU_F
CPU1
VDDQ3
CPU2
GND
CLK_STOP#
SDRAM16
VDDQ3
SDRAM0
SDRAM1
GND
SDRAM2
SDRAM3
SDRAM4
SDRAM5
VDDQ3
SDRAM6
SDRAM7
GND
SDRAM12
SDRAM13
VDDQ3
24MHz/FS0
48MHz/FS1
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
GND
SDATA
SCLK
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