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參數資料
| 型號： | CY28325OXC-3 |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | XO, clock |
| 英文描述： | 1206 SIZE 100NF 100V X7R +/- 10% |
| 中文描述： | 200.5 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封裝： | LEAD FREE, SSOP-48 |
| 文件頁數： | 1/19頁 |
| 文件大?。?/td> | 266K |
| 代理商： | CY28325OXC-3 |
FTG for VIA Pentium 4 Chipsets
CY28325-3
Cypress Semiconductor Corporation
Document #: 38-07590 Rev. *.*
3901 North First Street
San Jose
,
CA 95134
408-943-2600
Revised May 12, 2004
Features
Spread Spectrum Frequency Timing Generator for VIA
PT/M 266-800 Pentium
4 Chipsets
Programmable clock output frequency with less than 1 MHz
increment
Integrated fail-safe Watchdog Timer for system recovery
Selectable hardware or software-programmed clock
frequency when Watchdog Timer time-out
Capable to generate system RESET after a Watchdog
Timer time-out occurs or a change in output frequency via
SMBus interface
Support SMBus Byte Read/Write and Block Read/Write
operations to simplify system BIOS development
Vendor ID and Revision ID support
Programmable-drive strength support
Programmable-output skew support
Three copies AGP Clocks
Power management control inputs
Available in 48-pin SSOP
Note:
1. Pins marked with [*] have internal pull-up resistors. Pins marked with[^] have internal pull-down resistors.
CPU
AGP
PCI
REF
APIC
48M
24_48M
x 3
x 3
x 9
x 1
x 2
x 1
x 1
~
Block Diagram
Pin Configuration
SSOP-48
VDD_REF
REF
XTAL
OSC
PLL Ref Freq
X2
X1
VDD_PCI
PCI_F
SCLK
PLL 1
SMBus
Logic
VDD_48MHz
48MHz
SDATA
VDD_AGP
AGP0:2
Divider
Network
VDD_CPU (3.3V)
CPUT_0,1, CPUC_0,1
Stop
Stop
PLL2
*(FS0:4)
2
*CPU_STOP#
*MULTSEL1
PD#
*PCI_STOP#
VTT_PWRGD#
*FS4/REF
VDD_REF
GND_REF
X1
X2
VDD_48MHz
*FS3/48MHz
*FS2/24_48MHz
GND_48MHz
*FS0/PCI_F
*FS1/PCI1
*MULT_SEL1/PCI2
GND_PCI
PCI3
PCI4
VDD_PCI
PCI5
PCI6
PCI7
GND_PCI
PCI8
*PD#
AGP0
VDD_AGP
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
28
27
26
25
VDD_APIC
GND_APIC
APIC0
APIC1
GND_CPU
VDD_CPU_CS(2.5V)
CPUT_CS_F
CPUC_CS_F
CPUT_0
CPUC_0
VDD_CPU(3.3V)
IREF
GND_CPU
CPUT_1
CPUC_1
VTT_PWRGD#
CPU_STOP#*
PCI_STOP#*
RST#
SDATA
SCLK
AGP2
AGP1
GND_AGP
C
PCI1:8
24_48MHz
RST#
VDD_APIC
APIC0:1
CPUT_CS, CPUC_CS
VDD_CPU_CS (2.5V)
[1]
相關PDF資料 |
PDF描述 |
|---|---|
| CY28325OXC-3T | 0.1UF, 10%, 50V, X7R CAP, X7R, 50V, 1206 |
| CY28325OC-3 | CAP,SM,CER,.01UF,50V,10%,X7R |
| CY28343 | Zero Delay SDR/DDR Clock Buffer |
| CY28343OC | Zero Delay SDR/DDR Clock Buffer |
| CY28343OCT | Zero Delay SDR/DDR Clock Buffer |
相關代理商/技術參數 |
參數描述 |
|---|---|
| CY28325OXC-3T | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:FTG for VIA Pentium 4 Chipsets |
| CY28326 | 制造商:SPECTRALINEAR 制造商全稱:SPECTRALINEAR 功能描述:FTG for VIA PT880 Serial Chipset |
| CY28326OC | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:FTG for VIA PT880 Serial Chipset |
| CY28326OCT | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:FTG for VIA PT880 Serial Chipset |
| CY28326OXC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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