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參數資料
| 型號： | CY28343OCT |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 時鐘及定時 |
| 英文描述： | Zero Delay SDR/DDR Clock Buffer |
| 中文描述： | PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 6 INVERTED OUTPUT(S), PDSO48 |
| 封裝： | SSOP-48 |
| 文件頁數： | 1/10頁 |
| 文件大小： | 91K |
| 代理商： | CY28343OCT |
Zero Delay SDR/DDR Clock Buffer
CY28343
Cypress Semiconductor Corporation
Document #: 38-07369 Rev. *A
3901 North First Street
San Jose
CA 95134
Revised December 26, 2002
408-943-2600
Features
Phase-lock loop clock distribution for DDR and SDR
SDRAM applications
One-single-end clock input to 6 pairs DDR outputs or
13 SDR outputs.
External feedback pins FBIN_SDR/FBOUT_SDR are
used to synchronize the outputs to the clock input for
SDR.
External feedback pins FBIN_SDR/FBOUT_SDR are
used to synchronize the outputs to the clock input for
DDR.
SMBus interface enables/disables outputs.
Conforms to JEDEC SDR/DDR specifications
Low jitter, low skew
48 pin SSOP package
Note:
1.
Pins marked with [*] have internal pull-down resistors. Pins marked with [**] have internal pull-up resistors.
Table 1. Function Table
SELDDR_SDR#
1= DDR Mode
CLKIN
2.5V
Compatible
SDRAM(0:12)
OFF
DDRT/C(0:5)
Active
2.5V
Compatible
OFF
FBIN_DDR
2.5V
Compatible
FBOUT_DDR
Active
2.5V
Compatible
OFF
FBIN_SDR
OFF
FBOUT_SDR
OFF
0 = SDRAM Mode
3.3V
Compatible
Active
3.3V
Compatible
OFF
Active
3.3V
Compatible
Active
3.3V
Compatible
Block Diagram
Pin Configuration
[1]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
VDD_3.3V
SDRAM0
SDRAM1
SDRAM2
SDRAM3
VSS
VDD_3.3V
SDRAM4
SDRAM5
CLKIN
SDRAM6
SDRAM7
VSS
VDD_3.3V
SDRAM8
SDRAM9
SDRAM10
SDRAM11
VSS
VDD_3.3V
SDRAM12
FBOUT_SDR
FBIN_SDR*
VSS
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
SELDDR_SDR#*
FBIN_DDR*
FBOUT_DDR
VDD_2.5V
DDRT5
DDRC5
DDRT4
DDRC4
VSS
VDD_2.5
DDRT3
DDRC3
DDRT2
DDRC2
VSS
VDD_2.5V
DDRT1
DDRC1
DDRT0
DDRC0
VSS
VDD_3.3V
SCLK**
SDATA**
FBOUT_DDR
DDRT(0:5)
DDRC(0:5)
Control
Logic
FBOUT_SDR
SDRAM (0:12)
SCLK
SDATA
PLL
*SELDDR_SDR
FBIN_DDR
CLKIN
FBIN_SDR
VDD_2.5V
VDD_3.3V
VDD_3.3V
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