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參數(shù)資料
| 型號： | CY28352OCT |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Differential Clock Buffer/Driver DDR400- and DDR333-Compliant |
| 中文描述： | 差分時鐘緩沖器/驅(qū)動器支持DDR400和DDR333內(nèi)存，兼容 |
| 文件頁數(shù)： | 1/7頁 |
| 文件大小： | 126K |
| 代理商： | CY28352OCT |
Differential Clock Buffer/Driver DDR400- and DDR333-Compliant
CY28352
Rev
1.0, November 21, 2006
2200 Laurelwood Road, Santa Clara, CA 95054
Page 1 of 7
Tel:(408) 855-0555
Fax:(408) 855-0550
www.SpectraLinear.com
Features
Supports 333 MHz and 400-MHz DDR SDRAM
60- 200 MHz operating frequency
Phase-locked loop (PLL) clock distribution for double
data rate synchronous DRAM applications
Distributes one clock input to six differential outputs
External feedback pin FBIN is used to synchronize
output to clock input
Conforms to DDRI specification
Spread Aware
for electromagnetic interference (EMI)
reduction
28-pin SSOP package
Description
This PLL clock buffer is designed for 2.5-V
DD
and 2.5-AV
DD
operation and differential output levels.
This device is a zero delay buffer that distributes a clock input
CLKIN to six differential pairs of clock outputs (CLKT[0:5],
CLKC[0:5]) and one feedback clock output FBOUT. The clock
outputs are controlled by the input clock CLKIN and the
feedback clock FBIN.
The two-line serial bus can set each output clock pair
(CLKT[0:5], CLKC[0:5]) to the Hi-Z state. When AV
DD
is
grounded, the PLL is turned off and bypassed for test
purposes.
The PLL in this device uses the input clock CLKIN and the
feedback clock FBIN to provide high-performance, low-skew,
low–jitter output differential clocks.
Block Diagram
Pin Configuration
28 pin SSOP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
GND
CLKC5
CLKT5
CLKC4
CLKT4
VDD
SDATA
NC
FBIN
FBOUT
NC
CLKT3
CLKC3
GND
CLKC0
CLKT0
VDD
CLKT1
CLKC1
GND
SCLK
CLKIN
AVDD
AGND
VDD
CLKT2
CLKC2
NC
C
Serial
Interface
Logic
SDATA
SCLK
CLKT0
CLKC0
CLKT1
CLKC1
FBOUT
CLKT2
CLKC2
CLKC3
CLKT3
CLKC4
CLKT4
CLKC5
CLKT5
PLL
FBIN
CLKIN
AVDD
10
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PDF描述 |
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| CY28352OXC | Differential Clock Buffer/Driver DDR400- and DDR333-Compliant |
| CY28352OXCT | Differential Clock Buffer/Driver DDR400- and DDR333-Compliant |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY28352OXC | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Differential Clock Buffer/Driver DDR400- and DDR333-Compliant |
| CY28352OXCT | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Differential Clock Buffer/Driver DDR400- and DDR333-Compliant |
| CY283530C-2 | 制造商:Cypress Semiconductor 功能描述: |
| CY28353-2 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Clocks and Buffers |
| CY28353OXC-2 | 功能描述:時鐘緩沖器 Differential clock Buffer/Driver RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
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