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參數(shù)資料
| 型號(hào)： | CY29351AI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | 2.5V or 3.3V, 200-MHz, 9-Output Zero Delay Buffer |
| 中文描述： | PLL BASED CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| 封裝： | 7 X 7 MM, 1 MM HEIGHT, PLASTIC, TQFP-32 |
| 文件頁(yè)數(shù)： | 1/8頁(yè) |
| 文件大?。?/td> | 286K |
| 代理商： | CY29351AI |
2.5V or 3.3V, 200-MHz, 9-Output Zero Delay Buffer
CY29351
Cypress Semiconductor Corporation
Document #: 38-07475 Rev. *A
3901 North First Street
San Jose
,
CA 95134
408-943-2600
Revised July 26, 2004
Features
Output frequency range: 25 MHz to 200 MHz
Input frequency range: 25 MHz to 200 MHz
2.5V or 3.3V operation
Split 2.5V/3.3V outputs
±2.5% max Output duty cycle variation
9 Clock outputs: Drive up to 18 clock lines
Two reference clock inputs: LVPECL or LVCMOS
150-ps max output-output skew
Phase-locked loop (PLL) bypass mode
Spread Aware
Output enable/disable
Pin-compatible with MPC9351
Industrial temperature range: –40°C to +85°C
32-Pin 1.0-mm TQFP package
Functional Description
The CY29351 is a low voltage high performance 200 MHz
PLL-based zero delay buffer designed for high speed clock
distribution applications.
The CY29351 features LVPECL and LVCMOS reference clock
inputs and provides 9 outputs partitioned in 4 banks of 1, 1, 2,
and 5 outputs. Bank A divides the VCO output by 2 or 4 while
the other banks divide by 4 or 8 per SEL(A:D) settings, see
Functional Table
. These dividers allow output to input ratios of
4:1, 2:1, 1:1, 1:2, and 1:4. Each LVCMOS compatible output
can drive 50
series or parallel terminated transmission lines.
For series terminated transmission lines, each output can
drive one or two traces giving the device an effective fanout of
1:18.
The PLL is ensured stable given that the VCO is configured to
run between 200 MHz to 500 MHz. This allows a wide range
of output frequencies from 25 MHz to 200 MHz. For normal
operation, the external feedback input, FB_IN, is connected to
one of the outputs. The internal VCO is running at multiples of
the input reference clock set by the feedback divider, see the
Table 1.
When PLL_EN is LOW, PLL is bypassed and the reference
clock directly feeds the output dividers. This mode is fully static
and the minimum input clock frequency specification does not
apply.
Block Diagram
Pin Configuration
Phase
Detector
LPF
÷2 / ÷4
÷4 / ÷8
÷4 / ÷8
÷4 / ÷8
QA
QB
QC0
QC1
QD0
QD1
QD2
QD3
QD4
SELA
PLL_EN
TCLK
REF_SEL
PECL_CLK
FB_IN
SELB
SELC
OE#
SELD
VCO
200 -
500 MHz
CY29351
R
P
T
V
Q
V
Q
V
P
V
Q
V
Q
V
Q
QC0
VDDQC
QC1
VSS
QD0
VDDQD
QD1
VSS
AVDD
FB_IN
SELA
SELB
SELC
SELD
AVSS
PECL_CLK
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
9
1
1
1
1
1
1
1
3
3
3
2
2
2
2
2
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY29351AIT | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:2.5V or 3.3V, 200-MHz, 9-Output Zero Delay Buffer |
| CY29351AXI | 功能描述:鎖相環(huán) - PLL 2.5/3.3V 200MHz IND RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| CY29351AXIT | 功能描述:鎖相環(huán) - PLL 2.5/3.3V 200MHz IND RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| CY29352 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:2.5V or 3.3V, 200-MHz, 11-Output Zero Delay Buffer |
| CY29352_07 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:2.5V or 3.3V, 200-MHz, 11-Output Zero Delay Buffer |
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