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參數資料
| 型號： | CY29352 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | D-Subminiature Connector; Gender:Female; No. of Contacts:80; D Sub Shell Size:DB80; Body Material:Zinc Alloy; Contact Material:Copper Alloy; Mounting Type:PCB Straight Thru Hole; Pitch Spacing:0.05"; Series:102; Lead Pitch:0.05" RoHS Compliant: Yes |
| 中文描述： | 2.5V或3.3V，200兆赫，11輸出零延遲緩沖器 |
| 文件頁數： | 1/8頁 |
| 文件大小： | 100K |
| 代理商： | CY29352 |
2.5V or 3.3V, 200-MHz, 11-Output
Zero Delay Buffer
CY29352
Cypress Semiconductor Corporation
Document #: 38-07476 Rev. **
3901 North First Street
San Jose
,
CA 95134
408-943-2600
Revised March 19, 2003
Features
Output frequency range: 16.67 MHz to 200 MHz
Input frequency range: 16.67 MHz to 200 MHz
2.5V or 3.3V operation
Split 2.5V/3.3V outputs
±2% max Output duty cycle variation
11 Clock outputs: Drive up to 22 clock lines
LVCMOS reference clock input
125-ps max output-output skew
PLL bypass mode
Spread Aware
Output enable/disable
Pin compatible with MPC9352 and MPC952
Industrial temperature range: –40°C to +85°C
32-Pin 1.0mm TQFP package
Description
The CY29352 is a low voltage high performance 200-MHz
PLL-based zero delay buffer designed for high speed clock
distribution applications.
The CY29352 features an LVCMOS reference clock input and
provides 11 outputs partitioned in 3 banks of 5, 4, and 2
outputs. Bank A divides the VCO output by 4 or 6 while Bank
B divides by 4 and 2 and Bank C divides by 2 and 4 per
SEL(A:C) settings, see
Function Table
. These dividers allow
output to input ratios of 3:1, 2:1, 3:2, 1:1, 2:3, 1:2, and 1:3.
Each LVCMOS compatible output can drive 50
series or
parallel terminated transmission lines. For series terminated
transmission lines, each output can drive one or two traces
giving the device an effective fanout of 1:22.
The PLL is ensured stable given that the VCO is configured to
run between 200 MHz to 500 MHz. This allows a wide range
of output frequencies from 16.67 MHz to 200 MHz. For normal
operation, the external feedback input, FB_IN, is connected to
one of the outputs. The internal VCO is running at multiples of
the input reference clock set by the feedback divider, see
Table 1.
When PLL_EN# is HIGH, PLL is bypassed and the reference
clock directly feeds the output dividers. This mode is fully static
and the minimum input clock frequency specification does not
apply.
Block Diagram
Pin Configuration
÷
2
÷4 /
÷6
QA0
QA1
QA2
QA3
QA4
VCO
200-500MHz
Phase
Detector
÷4 /
÷2
÷2 /
÷4
LPF
QB0
QB1
QB2
QB3
QC0
QC1
PLL_EN#
REFCLK
FB_IN
VCO_SEL
SELA
SELB
SELC
MR/OE#
CY29352
V
Q
Q
V
V
Q
Q
V
P
A
V
Q
V
Q
Q
V
VSS
QB1
QB0
VDDQB
VDDQA
QA4
QA3
VSS
VCO_SEL
SELC
SELB
SELA
MR/OE#
REFCLK
AVSS
FB_IN
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
9
1
1
1
1
1
1
1
3
3
3
2
2
2
2
2
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| CY29352AIT | HEADER,100POS, 0.050INC |
| CY29772 | 2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer |
| CY29772AI | 2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer |
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相關代理商/技術參數 |
參數描述 |
|---|---|
| CY29352_07 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:2.5V or 3.3V, 200-MHz, 11-Output Zero Delay Buffer |
| CY29352_08 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:2.5V or 3.3V, 200 MHz, 11 Output Zero Delay Buffer |
| CY29352_11 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:2.5 V or 3.3 V, 200 MHz, 11 Output Zero Delay Buffer |
| CY29352_12 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:2.5 V or 3.3 V, 200 MHz, 11 Output Zero Delay Buffer |
| CY29352AI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:2.5V or 3.3V, 200-MHz, 11-Output Zero Delay Buffer |
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