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參數資料
| 型號： | CY29774 |
| 英文描述： | Clocks and Buffers |
| 中文描述： | 時鐘和緩沖器 |
| 文件頁數： | 1/9頁 |
| 文件大小： | 74K |
| 代理商： | CY29774 |
2.5V or 3.3V, 125-MHz, 14 Output Zero Delay Buffer
CY29774
Cypress Semiconductor Corporation
Document #: 38-07479 Rev. **
3901 North First Street
San Jose
CA 95134
408-943-2600
Revised April 28, 2003
774
Features
Output frequency range: 8.3 MHz to 125 MHz
Input frequency range: 4.2 MHz to 62.5 MHz
2.5V or 3.3V operation
Split 2.5V/3.3V outputs
14 Clock outputs: Drive up to 28 clock lines
1 Feedback clock output
2 LVCMOS reference clock inputs
150 ps max output-output skew
PLL bypass mode
Spread Aware
Output enable/disable
Pin compatible with MPC9774
Industrial temperature range: –40°C to +85°C
52-Pin 1.0-mm TQFP package
Description
The CY29774 is a low-voltage high-performance 125-MHz
PLL-based zero delay buffer designed for high-speed clock
distribution applications.
The CY29774 features two reference clock inputs and pro-
vides 14 outputs partitioned in 3 banks of 5, 5, and 4 outputs.
Bank A and Bank B divide the VCO output by 4 or 8 while Bank
C divides by 8 or 12 per SEL(A:C) settings, see
Functional
Table
. These dividers allow output to input ratios of 6:1, 4:1,
3:1, 2:1, 3:2, 4:3, 1:1, and 2:3. Each LVCMOS compatible out-
put can drive 50
series or parallel terminated transmission
lines. For series terminated transmission lines, each output
can drive one or two traces giving the device an effective
fanout of 1:28.
The PLL is ensured stable given that the VCO is configured to
run between 200 MHz to 500 MHz. This allows a wide range
of output frequencies from 8.3 MHz to 125 MHz. For normal
operation, the external feedback input, FB_IN, is connected to
the feedback output, FB_OUT. The internal VCO is running at
multiples of the input reference clock set by the feedback di-
vider, see
Frequency Table.
When PLL_EN is LOW, PLL is bypassed and the reference
clock directly feeds the output dividers. This mode is fully static
and the minimum input clock frequency specification does not
apply.
Block Diagram
Pin Configuration
PLL
200 -
500MHz
÷
2 /
÷
4
÷
4 /
÷
6 /
÷
8 /
÷
12
QA0
QA1
QA2
QA3
QA4
QB0
QB1
QB2
QB3
QB4
QC0
QC1
QC2
QC3
FB_OUT
SELA
VCO_SEL
PLL_EN
TCLK0
TCLK1
TCLK_SEL
FB_IN
SELB
SELC
MR#/OE
FB_SEL(1,0)
÷
2
÷
4
CLK
÷
2 /
÷
4
CLK
÷
4 /
÷
6
CLK
CLK_STP#
VSS
MR#/OE
CLK_STP#
SELB
SELC
PLL_EN
SELA
TCLK_SEL
TCLK0
TCLK1
NC
VDD
AVDD
V
Q
V
Q
V
Q
F
V
Q
V
Q
A
F
Q
V
N
V
Q
V
Q
V
Q
V
Q
V
V
VSS
QB1
VDDQB
QB2
VSS
QB3
VDDQB
QB4
FB_IN
VSS
FB_OUT
VDDFB
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
39
38
37
36
35
34
33
32
31
30
29
28
27
14 15 16 17 18 19 20 21 22 23 24 25 26
52 51 50 49 48 47 46 45 44 43 42 41 40
CY29774
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PDF描述 |
|---|---|
| CY29775 | Clocks and Buffers |
| CY29940-1 | Clocks and Buffers |
| CY29976 | Clocks and Buffers |
| CY29977 | Clocks and Buffers |
| CY29FCT520ATDM | Pipeline Register |
相關代理商/技術參數 |
參數描述 |
|---|---|
| CY29774AI | 制造商:Cypress Semiconductor 功能描述:Zero Delay PLL Clock Buffer Single 52-Pin TQFP |
| CY29774AIT | 制造商:Cypress Semiconductor 功能描述: |
| CY29774AXI | 功能描述:鎖相環 - PLL ZERO DELAY PLL 125 MHz 14 OUTPUT RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| CY29774AXIT | 功能描述:鎖相環 - PLL ZERO DELAY PLL 125 MHz 14 OUTPUT RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| CY29775 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Clocks and Buffers |
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