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參數(shù)資料
| 型號(hào)： | CY2V9950 |
| 英文描述： | Clocks and Buffers |
| 中文描述： | 時(shí)鐘和緩沖器 |
| 文件頁(yè)數(shù)： | 1/9頁(yè) |
| 文件大小： | 164K |
| 代理商： | CY2V9950 |
2.5/3.3V 200-MHz Multi-output Zero Delay Buffer
CY2V9950
Cypress Semiconductor Corporation
Document #: 38-07436 Rev. **
3901 North First Street
San Jose
,
CA 95134
408-943-2600
Revised January 9, 2003
Features
2.5V or 3.3V operation
Split output bank power supplies
Output frequency range: 6 MHz to 200 MHz
Output-output skew < 150 ps
Cycle-cycle jitter < 100 ps
Selectable positive or negative edge synchronization
Selectable phase-locked loop (PLL) frequency range
8 LVTTL outputs driving 50
terminated lines
LVCMOS/LVTTL Over-voltage tolerant reference input
2x, 4x multiply and (1/2)x, (1/4)x divide ratios
Spread-Spectrum-compatible
Pin-compatible with IDT5V9950 and IDT5T9950
Industrial temperature range:
–
40
°
C to +85
°
C
32-pin TQFP package
Description
The CY2V9950 is a low-voltage, low-power, eight-output,
200-MHz clock driver. It features functions necessary to
optimize the timing of high performance computer and
communication systems.
The user can program the output banks through 3F[0:1] and
4F[0:1]pins. Any one of the outputs can be connected to
feedback input to achieve different reference frequency multi-
plication and divide ratios and zero input-output delay.
The device also features split output bank power supplies
which enable the user to run two banks (1Qn and 2Qn) at a
power supply level different from that of the other two banks
(3Qn and 4Qn). Additionally, the PE pin controls the synchro-
nization of the output signals to either the rising or the falling
edge of the reference clock.
Block Diagram
Pin Configuration
3
F
V
R
V
T
2
2
CY2V9950
32 31 30 29 28 27 26 25
9 10 11 12 13 14 15 16
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
1F1
1F0
sOE#
VDDQ1
1Q0
1Q1
VSS
VSS
3F1
4F0
4F1
PE
VDDQ4
4Q0
VSS
4Q1
V
3
3
V
2
F
V
2
PE
TEST
FS
3
3
REF
FB
2F1:0
1F1:0
3F1:0
4F1:0
1Q0
1Q1
2Q0
2Q1
3Q0
3Q1
4Q0
4Q1
PLL
3
3
3
3
/ K
sOE#
VDDQ1
VDDQ4
/ M
VDDQ3
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY2V9950AC | 制造商:Rochester Electronics LLC 功能描述:2.5/3.3V 200 MHZ LVCMOS INPUT, 8 OUTPUT ZDB - Bulk |
| CY2V9950ACT | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:2.5/3.3V 200-MHz Multi-Output Zero Delay Buffer |
| CY2V9950AI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:2.5/3.3V 200-MHz Multi-Output Zero Delay Buffer |
| CY2V9950AIT | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:2.5/3.3V 200-MHz Multi-Output Zero Delay Buffer |
| CY2V995AC | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:S2.5/3.3V 200-MHz Multi-Output Zero Delay Buffer |
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