- 您現在的位置：買賣IC網 > PDF目錄366979 > CY3125R62 Programmable Logic PDF資料下載
參數資料
| 型號： | CY3125R62 |
| 英文描述： | Programmable Logic |
| 中文描述： | 可編程邏輯 |
| 文件頁數： | 1/8頁 |
| 文件大小： | 67K |
| 代理商： | CY3125R62 |
Warp
CPLD Development Software for PC
CY3120
Cypress Semiconductor Corporation
Document #: 38-03049 Rev. *C
3901 North First Street
San Jose
,
CA 95134
408-943-2600
Revised August 18, 2002
Features
VHDL (IEEE 1076 and 1164) and Verilog (IEEE 1364)
high-level language compilers with the following
features
—Designs are portable across multiple devices
and/or EDA environments
—Facilitates the use of industry-standard simulation
and synthesis tools for board and system-level
design
—Support for functions and libraries facilitating
modular design methodology
IEEE Standard 1076 and 1164 VHDL synthesis supports
—Enumerated types
—Operator overloading
—For... Generate statements
—Integers
IEEE Standard 1364 Verilog synthesis supports
—Reduction and conditional operators
—Blocking and non-blocking procedural assignments
—While loops
—Integers
Several design entry methods support high-level and
low-level design descriptions
—Behavioral VHDL and Verilog (IF...THEN...ELSE;
CASE...)
—Boolean
—Aldec Active-HDL FSM graphical Finite State
Machine editor
—Structural Verilog and VHDL
—Designs can include multiple entry methods (but
only one HDL language) in a single design
UltraGen Synthesis and Fitting Technology
—Infers “modules” such as adders, comparators, etc.,
from behavioral descriptions and replaces them with
circuits pre-optimized for the target device
—User selectable speed and/or area optimization on a
block-by-block basis
—Perfect communication between synthesis and
fitting
—Automatic selection of optimal flip-flop type
(D type/T type)
—Automatic pin assignment
Ability to specify timing constraints for all of the
Delta39K and PSI devices
Supports all Cypress Programmable Logic Devices
—PSI (Programmable Serial Interface)
—Delta39K Complex Programmable Logic Devices
(CPLDs)
—Ultra37000 CPLDs
—F
LASH
370i CPLDs
—MAX340 CPLDs
—Industry standard PLDs (16V8, 20V8, 22V10)
VHDL and Verilog timing model output for use with
third-party simulators
Timing simulation provided by Active-HDL Sim
Release 3.3 from Aldec
—Graphical waveform simulator
—Entry and modification of on-screen waveforms
—Ability to probe internal nodes
—Display of inputs, outputs, and high impedance (Z)
signals in different colors
—Automatic clock and pulse creation
—Support for buses
Architecture Explorer and Dynamic Timing Analysis for
PSI and Delta39K devices
—Graphical representation of exactly how your design
will be implemented on your specific target device
—Zoom from the device level down to the macrocell
level
—Determine the timing for any path and view that path
on a graphical representation of the chip
Static Timing Report for all devices
PC Support (Windows 98, Windows NT 4.0, and
Windows XP)
On-line documentation and help
相關PDF資料 |
PDF描述 |
|---|---|
| CY3128R62 | Programmable Logic |
| CY3130R62 | Programmable Logic |
| CY3138R62 | Programmable Logic |
| CY325B | LCD Controller |
| CY338003 | ASIC |
相關代理商/技術參數 |
參數描述 |
|---|---|
| CY3128 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Warp Professional CPLD Software |
| CY3128R62 | 制造商:Cypress Semiconductor 功能描述: |
| CY3130 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Warp Enterprise⑩ VHDL CPLD Software |
| CY3130R62 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Warp Enterprise⑩ VHDL CPLD Software |
| CY3138 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Warp Enterprise⑩ Verilog CPLD Software |
發布緊急采購，3分鐘左右您將得到回復。