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參數(shù)資料
| 型號： | CY62136EV30LL-45ZSXI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 2-Mbit (128K x 16) Static RAM |
| 中文描述： | 128K X 16 STANDARD SRAM, 45 ns, PDSO44 |
| 封裝： | LEAD FREE, TSOP2-44 |
| 文件頁數(shù)： | 1/12頁 |
| 文件大小： | 567K |
| 代理商： | CY62136EV30LL-45ZSXI |
2-Mbit (128K x 16) Static RAM
CY62136EV30
MoBL
Cypress Semiconductor Corporation
Document #: 38-05569 Rev. *B
198 Champion Court
San Jose
,
CA 95134-1709
408-943-2600
Revised January 6, 2006
Features
Very high speed: 45 ns
Wide voltage range: 2.20V–3.60V
Pin-compatible with CY62136CV30
Ultra low standby power
— Typical standby current: 1
μ
A
— Maximum standby current: 7
μ
A
Ultra-low active power
— Typical active current: 2 mA @ f = 1 MHz
Easy memory expansion with CE, and OE features
Automatic power-down when deselected
CMOS for optimum speed/power
Offered in a Pb-free 48-ball VFBGA and 44-pin TSOP II
packages
Functional Description
[1]
The CY62136EV30 is a high-performance CMOS static RAM
organized as 128K words by 16 bits. This device features
advanced circuit design to provide ultra-low active current.
This is ideal for providing More Battery Life (MoBL
) in
portable applications such as cellular telephones. The device
also has an automatic power-down feature that significantly
reduces power consumption by 80% when addresses are not
toggling. The device can also be put into standby mode
reducing power consumption by more than 99% when
deselected (CE HIGH). The input/output pins (I/O
0
through
I/O
15
) are placed in a high-impedance state when: deselected
(CE HIGH), outputs are disabled (OE HIGH), both Byte High
Enable and Byte Low Enable are disabled (BHE, BLE HIGH),
or during a write operation (CE LOW and WE LOW).
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O
0
through I/O
7
), is
written into the location specified on the address pins (A
0
through A
16
). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O
8
through I/O
15
) is written into the location
specified on the address pins (A
0
through A
16
).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O
0
to I/O
7
. If Byte High Enable (BHE) is
LOW, then data from memory will appear on I/O
8
to I/O
15
. See
the truth table at the back of this data sheet for a complete
description of read and write modes.
Note:
1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
Logic Block Diagram
128K x 16
RAM Array
I/O
0
–I/O
7
R
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
COLUMN DECODER
A
1
A
1
A
1
A
1
A
1
S
DATA IN DRIVERS
OE
BLE
I/O
8
–I/O
15
CE
WE
BHE
A
1
A
0
A
9
A
10
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相關PDF資料 |
PDF描述 |
|---|---|
| CY62136FV30 | 2-Mbit (128K x 16) Static RAM |
| CY62136FV30LL | 2-Mbit (128K x 16) Static RAM |
| CY62136FV30LL-45BVXI | 2-Mbit (128K x 16) Static RAM |
| CY62136FV30LL-45ZSXI | 2-Mbit (128K x 16) Static RAM |
| CY62136FV30LL-55ZSXE | 2-Mbit (128K x 16) Static RAM |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| CY62136EV30LL-45ZSXI | 制造商:Cypress Semiconductor 功能描述:IC SRAM 2MBIT PARALLEL 45NS TSOP-44 制造商:Cypress Semiconductor 功能描述:IC, SRAM, 2MBIT, PARALLEL, 45NS, TSOP-44 |
| CY62136EV30LL-45ZSXIT | 功能描述:靜態(tài)隨機存取存儲器 SLO 3.0V SUPER LO PWR 128KX16 靜態(tài)隨機存取存儲器 IND RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY62136FV30 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:2-Mbit (128 K x 16) Static RAM Automatic power down when deselected |
| CY62136FV30_09 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:2 Mbit (128K x 16) Static RAM |
| CY62136FV30_11 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:2-Mbit (128 K x 16) Static RAM Automatic power down when deselected |
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