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參數資料
| 型號： | CY62147V18 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 256K x 16 Static RAM(256K x 16靜態RAM) |
| 中文描述： | 256K × 16靜態RAM（256K × 16靜態RAM）的 |
| 文件頁數： | 1/11頁 |
| 文件大小： | 197K |
| 代理商： | CY62147V18 |
256K x 16 Static RAM
CY62147V MoBL
CY62147V18 MoBL2
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
December 21, 1999
Features
Low voltage range:
—CY62147V: 1.65V–1.95V
—CY62147V18: 2.7V–3.6V
Ultra-low active, standby power
Easy memory expansion with CE and OE features
TTL-compatible inputs and outputs
Automatic power-down when deselected
CMOS for optimum speed/power
Functional Description
The CY62147V and CY62147V18 are high-performance
CMOS static RAMs organized as 262,144 words by 16 bits.
These devices feature advanced circuit design to provide ul-
tra-low active current. This is ideal for providing More Battery
Life (MoBL) in portable applications such as cellular tele-
phones. The devices also have an automatic power-down fea-
ture that significantly reduces power consumption by 99%
when addresses are not toggling. The device can also be put
into standby mode when deselected (CE HIGH) or when CE
is LOW and both BLE and BHE are HIGH. The input/output
pins (I/O
0
through I/O
15
) are placed in a high-impedance state
when: deselected (CE HIGH), outputs are disabled (OE
HIGH), BHE and BLE are disabled (BHE, BLE HIGH), or dur-
ing a write operation (CE LOW, and WE LOW).
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O
0
through I/O
7
), is
written into the location specified on the address pins (A
0
through A
17
). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O
8
through I/O
15
) is written into the location
specified on the address pins (A
0
through A
17
).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O
0
to I/O
7
. If Byte High Enable (BHE) is
LOW, then data from memory will appear on I/O
8
to I/O
15
. See
the truth table at the back of this data sheet for a complete
description of read and write modes.
The CY62147V and CY62147V18 are available in 48-ball
FBGA and standard 44-pin TSOP Type II (forward pinout)
packaging.
MoBL and More Battery Life are trademarks of Cypress Semiconductor Corporation.
Logic Block Diagram
Pin Configurations
WE
A
16
A
15
A
14
A
13
A
12
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
31
30
32
36
35
34
33
37
40
39
38
Top View
41
44
43
42
16
17
29
28
V
CC
V
SS
I/O
4
I/O
5
A
4
A
3
A
2
A
1
A
0
OE
BHE
BLE
V
SS
V
CC
I/O
11
I/O
10
I/O
9
I/O
8
A
5
A
6
A
7
I/O
15
I/O
14
I/O
13
I/O
12
CE
I/O
0
I/O
1
I/O
2
I/O
3
NC
A
8
A
9
A
10
A
11
A
17
18
19
20
21
27
26
25
24
22
23
I/O
6
I/O
7
62147V–2
TSOP II (Forward)
256K x 16
RAM Array
2048 x 2048
I/O
0
– I/O
7
R
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
COLUMN DECODER
A
1
A
1
A
1
A
1
A
1
S
DATA IN DRIVERS
OE
BLE
I/O
8
– I/O
15
CE
WE
BHE
A
1
62147V–1
A
1
A
0
A
1
A
9
Power
-
Down
Circuit
BHE
BLE
CE
相關PDF資料 |
PDF描述 |
|---|---|
| CY62147V | 4M (256K x 16) Static RAM |
| CY62147VLL-70ZI | 4M (256K x 16) Static RAM |
| CY62148-55 | 512K x 8 Static RAM |
| CY62148-55SC | 512K x 8 Static RAM |
| CY62148-70 | 512K x 8 Static RAM |
相關代理商/技術參數 |
參數描述 |
|---|---|
| CY62147V18-85BAI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x16 SRAM |
| CY62147V18LL-70BAI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x16 SRAM |
| CY62147VLL-70BAI | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Async Single 3V 4M-Bit 256K x 16 70ns 48-Pin FBGA |
| CY62147VLL-70BAIT | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Async Single 3V 4M-Bit 256K x 16 70ns 48-Pin FBGA T/R |
| CY62147VLL-70ZI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:4M (256K x 16) Static RAM |
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