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參數(shù)資料
| 型號(hào)： | CY62148-55SC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 512K x 8 Static RAM |
| 中文描述： | 512K X 8 STANDARD SRAM, 55 ns, PDSO32 |
| 封裝： | 0.450 INCH, PLASTIC, SOIC-32 |
| 文件頁(yè)數(shù)： | 1/7頁(yè) |
| 文件大小： | 200K |
| 代理商： | CY62148-55SC |
512K x 8 Static RAM
fax id: 1079
CY62148
PRELIMINARY
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
December 1996 - Revised July 31, 1997
1CY62148
Features
4.5V
5.5V operation
CMOS for optimum speed/power
Low active power
—660 mW (max.)
Low standby power (L version)
—2.75 mW (max.)
Automatic power-down when deselected
TTL-compatible inputs and outputs
Easy memory expansion with CE
and OE options
Functional Description
The CY62148 is a high-performance CMOS static RAM orga-
nized as 524,288 words by 8 bits. Easy memory expansion is
provided by an active LOW chip enable (CE), an active LOW
output enable (OE), and three-state drivers. This device has
an automatic power-down feature that reduces power con-
sumption by more than 99% when deselected.
Writing to the device is accomplished by taking chip enable
one (CE) and write enable (WE) inputs LOW. Data on the eight
I/O pins (I/O
0
through I/O
7
) is then written into the location
specified on the address pins (A
0
through A
18
).
Reading from the device is accomplished by taking chip en-
able one (CE) and output enable (OE) LOW while forcing write
enable (WE). Under these conditions, the contents of the
memory location specified by the address pins will appear on
the I/O pins.
The eight input/output pins (I/O
0
through I/O
7
) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE LOW, and WE LOW).
The CY62148 is available in a standard 450-mil-wide body
width SOIC package.
Selection Guide
CY62148–55
55
120 mA
2 mA
0.5 mA
CY62148–70
70
120 mA
2 mA
0.5 mA
Maximum Access Time (ns)
Maximum Operating Current
Maximum CMOS Standby Current
Commercial
Commercial
L
Shaded areas contain advance information
1
A
1
A
Logic Block Diagram
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
COLUMN
DECODER
R
S
INPUT BUFFER
POWER
DOWN
WE
OE
I/O
0
I/O
1
I/O
2
I/O
3
512K x 8
ARRAY
I/O
7
I/O
6
I/O
5
I/O
4
A
0
A
1
A
1
A
1
A
10
CE
A
1
62148-1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
19
18
20
24
23
22
21
25
28
27
26
Top View
SOIC
29
32
31
30
16
17
GND
A
16
A
14
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
WE
A
13
A
8
A
9
A
11
V
CC
A
15
A
18
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
I/O
0
I/O
1
I/O
2
CE
OE
A
10
A
1
A
1
A
17
Pin Configuration
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY62148-70 | 512K x 8 Static RAM |
| CY62148L-55SC | 512K x 8 Static RAM |
| CY62148BLL-70ZRI | Circular Connector; MIL SPEC:MIL-C-26482, Series I, Solder; Body Material:Aluminum; Series:PT02; Number of Contacts:6; Connector Shell Size:10; Connecting Termination:Solder; Circular Shell Style:Box Mount Receptacle |
| CY62148B | 512K x 8 Static RAM |
| CY62148BLL-70SC | 512K x 8 Static RAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY62148-70 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:512K x 8 Static RAM |
| CY62148-70SC | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:512K x 8 MoBL Static RAM |
| CY62148-70SI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SRAM |
| CY62148-70ZSC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SRAM |
| CY62148-70ZSI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SRAM |
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