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參數資料
| 型號： | CY62157EV30LL-45BVXI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 8-Mbit (512K x 16) Static RAM |
| 中文描述： | 512K X 16 STANDARD SRAM, 45 ns, PBGA48 |
| 封裝： | 6 X 8 MM, 1 MM HEIGHT, LEAD FREE, VFBGA-48 |
| 文件頁數： | 1/14頁 |
| 文件大?。?/td> | 551K |
| 代理商： | CY62157EV30LL-45BVXI |
8-Mbit (512K x 16) Static RAM
CY62157EV30 MoBL
Cypress Semiconductor Corporation
Document #: 38-05445 Rev. *E
198 Champion Court
San Jose
,
CA 95134-1709
408-943-2600
Revised May 07, 2007
Features
TSOP I package configurable as 512K x 16 or as 1M x 8
SRAM
High speed: 45 ns
Wide voltage range: 2.20V–3.60V
Pin compatible with CY62157DV30
Ultra low standby power
— Typical Standby current: 2
μ
A
— Maximum Standby current: 8
μ
A (Industrial)
Ultra low active power
— Typical active current: 1.8 mA @ f = 1 MHz
Easy memory expansion with CE
1
, CE
2
, and OE features
Automatic power down when deselected
CMOS for optimum speed and power
Available in both Pb-free and non Pb-free 48-ball VFBGA,
Pb-free 44-pin TSOP II and 48-pin TSOP I packages
Functional Description
[1]
The CY62157EV30 is a high performance CMOS static RAM
organized as 512K words by 16 bits. This device features
advanced circuit design to provide ultra low active current.
This is ideal for providing More Battery Life
(MoBL
) in
portable applications such as cellular telephones. The device
also has an automatic power down feature that significantly
Logic Block Diagram
reduces power consumption when addresses are not toggling.
Place the device into standby mode when deselected (CE
1
HIGH or CE
2
LOW or both BHE and BLE are HIGH). The input
or output pins (IO
0
through IO
15
) are placed in a high
impedance state when:
Deselected (CE
1
HIGH or CE
2
LOW)
Outputs are disabled (OE HIGH)
Both Byte High Enable and Byte Low Enable are disabled
(BHE, BLE HIGH)
Write operation is active (CE
1
LOW, CE
2
HIGH and WE
LOW)
To write to the device, take Chip Enable (CE
1
LOW and CE
2
HIGH) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from IO pins (IO
0
through IO
7
) is
written into the location specified on the address pins (A
0
through A
18
). If Byte High Enable (BHE) is LOW, then data
from IO pins (IO
8
through IO
15
) is written into the location
specified on the address pins (A
0
through A
18
).
To read from the device, take Chip Enable (CE
1
LOW and CE
2
HIGH) and Output Enable (OE) LOW while forcing the Write
Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then
data from the memory location specified by the address pins
appear on IO
0
to IO
7
. If Byte High Enable (BHE) is LOW, then
data from memory appears on IO
8
to IO
15
. See the
“Truth
Table” on page 10
for a complete description of read and write
modes.
512K × 16 / 1M x 8
RAM Array
IO
0
–IO
7
R
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
COLUMN DECODER
A
1
A
1
A
1
A
1
A
1
S
DATA IN DRIVERS
OE
IO
8
–IO
15
WE
BLE
BHE
A
1
A
0
A
1
A
9
A
1
A
10
Power Down
Circuit
BHE
BLE
CE
2
CE
1
CE
2
CE
1
BYTE
Notes
1. For best practice recommendations, please refer to the Cypress application note
AN1064, SRAM System Guidelines
.
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相關代理商/技術參數 |
參數描述 |
|---|---|
| CY62157EV30LL-45BVXIT | 功能描述:靜態隨機存取存儲器 8M ULTRA LO PWR HI SPD 靜態隨機存取存儲器 IND RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY62157EV30LL-45BVXIT NOVATECH | 制造商:Cypress Semiconductor 功能描述: |
| CY62157EV30LL-45XIKA | 制造商:Cypress Semiconductor 功能描述: |
| CY62157EV30LL-45XIKU | 制造商:Cypress Semiconductor 功能描述: |
| CY62157EV30LL-45ZSXA | 功能描述:靜態隨機存取存儲器 8M MOBL ULTRA Lo PWR HI SPD ASYNC 靜態隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
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