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參數(shù)資料
| 型號(hào)： | CY62167DV18LL-70 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 4NC Direct Opening |
| 中文描述： | 1,600（1024K × 16）靜態(tài)RAM |
| 文件頁(yè)數(shù)： | 1/11頁(yè) |
| 文件大小： | 161K |
| 代理商： | CY62167DV18LL-70 |
16M (1024K x 16) Static RAM
PRELIMINARY
CY62167DV18
MoBL2
Cypress Semiconductor Corporation
Document #: 38-05326 Rev. *A
3901 North First Street
San Jose
,
CA 95134
408-943-2600
Revised February 10, 2003
Features
Very high speed: 55 ns and 70 ns
Voltage range: 1.65V
to
1.95V
Ultra-low active power
—
Typical active current: 1.5 mA @ f = 1 MHz
—
Typical active current: 15 mA @ f = f
MAX
Ultra-low standby power
Easy memory expansion with CE</>
1</>, CE2</> and OE</>
features
Automatic power-down when deselected
CMOS for optimum speed/power
Packages offered in a 48-ball FBGA
Functional Description
[1]
The CY62167DV18 is a high-performance CMOS static RAM
organized as 1024K words by 16 bits. This device features
advanced circuit design to provide ultra-low active current.
This is ideal for providing More Battery Life
(MoBL
) in
portable applications such as cellular telephones. The device
also has an automatic power-down feature that significantly
reduces power consumption by 99% when addresses are not
toggling. The device can be put into standby mode reducing
power consumption by more than 99% when deselected Chip
Enable 1 (CE
1
) HIGH or Chip Enable 2 (CE
2
) LOW or both
BHE and BLE are HIGH. The input/output pins (I/O
0
through
I/O
15
) are placed in a high-impedance state when: deselected
Chip Enable 1 (CE
1
) HIGH or Chip Enable 2 (CE
2
) LOW,
outputs are disabled (OE HIGH), both Byte High Enable and
Byte Low Enable are disabled (BHE, BLE HIGH) or during a
write operation (Chip Enable 1 (CE
1
) LOW and Chip Enable 2
(CE
2
) HIGH and WE LOW).
Writing to the device is accomplished by taking Chip Enable 1
(CE
1
) LOW and Chip Enable 2 (CE
2
) HIGH and Write Enable
(WE) input LOW. If Byte Low Enable (BLE) is LOW, then das
pins (A
0
through A
19
). If Byte High Enable (BHE) is LOW, then
data from I/O pins (I/O
8
through I/O
15
) is written into the
location specified on the ad
Reading from the device is accomplished by taking Chip
Enable 1 (CE
1
) LOW and Chip Enable 2 (CE
2
) HIGH and
Output Enable (OE) LOW while forcing the Write Enable (WE)
HIGH. If Byte Low Enable (<>O
7
. If Byte High Enable (BHE)
is LOW, then data from memory will appear on I/O
8
to I/O
15
.
See the truth table at the back of this data sheet for a complete
description of read and write modes.
Note:
1.
For best practice recommendations, please refer to the Cypress application note
“
System Design Guidelines
”
on http://www.cypress.com.
1024K x 16
RAM ARRAY
2048 x 512 x 16
I/O
0
–I/O
7
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
C OLUMN DEC ODER
A
1
A
1
A
1
A
1
A
1
S
DATA IN DRIVERS
OE
I/O
8
–I/O
15
WE
BLE
BHE
A
1
A
0
A
1
A
9
A
1
A
10
Power-down
C ircuit
BHE
BLE
C E
2
C E
1
C E
2
C E
1
A
1
Logic Block Diagram
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY62167DV20L | 16-Mb (1024K x 16) Static RAM |
| CY62167DV20L-55BVI | 16-Mb (1024K x 16) Static RAM |
| CY62167DV20L-70BVI | 16-Mb (1024K x 16) Static RAM |
| CY62167DV20LL | 16-Mb (1024K x 16) Static RAM |
| CY62167DV20LL-55BVI | 16-Mb (1024K x 16) Static RAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY62167DV18LL-70BVI | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Async Single 1.8V 16M-Bit 1M x 16 70ns 48-Pin VFBGA 制造商:Rochester Electronics LLC 功能描述:16M (1M X 16)- 1.8V SLOW ASYNCH SRAM - Bulk |
| CY62167DV20L-70BVI | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Async Single 3.3V 16M-Bit 1M x 16 70ns 48-Pin VFBGA |
| CY62167DV20LL-55BVI | 制造商:Rochester Electronics LLC 功能描述:16M (1M X 16)- 2.0V SLOW ASYNCH SRAM - Bulk |
| CY62167DV20LL-5BVI | 制造商:Cypress Semiconductor 功能描述: |
| CY62167DV30L-70BVI | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Async Single 3V 16M-Bit 1M x 16 70ns 48-Pin VFBGA |
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